LP5521TMEV National Semiconductor, LP5521TMEV Datasheet - Page 35

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LP5521TMEV

Manufacturer Part Number
LP5521TMEV
Description
EVAL BOARD FOR LP5521
Manufacturer
National Semiconductor
Datasheets

Specifications of LP5521TMEV

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q5109809
Configuration Control (CONFIG)
Address 08H
Reset value 00H
R Channel Program Counter Value (R channel PC)
Address 09H
Reset value 00H
PC registers are synchronized to 32 kHz clock. Delay between consecutive I
μs (typ.). PC register can be read or written only when EXEC mode is 'hold'.
PWRSAVE_EN
CLK_DET_EN,
INT_CLK_EN
R_TO_BATT
CP_MODE
Name
R_PC
PWM_HF
Name
7
7
PWM_HF
Bit
3:0
6
6
Bit
4:3
1:0
6
5
2
Access
PWRSAVE_EN
R/W
5
5
Access
R/W
R/W
R/W
R/W
R/W
Active
R Channel PC Register
CONFIG Register
4
4
CP_MODE[1:0]
Description
R channel program counter value
Active
High
High
High
35
R_PC[3]
3
3
Description
PWM clock
0 = 256 Hz PWM clock used (CLK_32K)
1 = 558 Hz PWM clock used (internal oscillator)
Power save mode enable
Charge pump operation mode
00b = OFF
01b = Forced to bypass mode (1x)
10b = Forced to 1.5x mode
11b = Automatic mode selection
R channel supply connection
0 = R output connected to charge pump
1 = R output connected to battery
LED Controller clock source
00b = External clock source (CLK_32K)
01b = Internal clock
10b = Automatic selection
11b = Internal clock
2
C writes to PC registers needs to be longer than 153
R_TO_BATT
R_PC[2]
2
2
CLK_DET_EN INT_CLK_EN
R_PC[1]
1
1
R_PC[0]
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0
0

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