LP5521TMEV National Semiconductor, LP5521TMEV Datasheet - Page 25

• Manufacturer Part Number: LP5521TMEV
• Description: EVAL BOARD FOR LP5521
• Manufacturer: National Semiconductor

Specifications of LP5521TMEV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5109809

Before any data is transmitted, the master transmits the ad-
dress of the slave being addressed. The slave device should
send an acknowledge signal on the SDA line, once it recog-
nizes its address.
The slave address is the first seven bits after a Start Condi-
tion. The direction of the data transfer (R/W) depends on the
bit sent after the slave address — the eighth bit.
When the slave address is sent, each device in the system
compares this slave address with its own. If there is a match,
the device considers itself addressed and sends an acknowl-
edge signal. Depending upon the state of the R/W bit (1:read,
0:write), the device acts as a transmitter or a receiver.
Control Register Write Cycle
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Master device generates start condition.
Master device sends slave address (7 bits) and the data
direction bit (r/w = 0).
Slave device sends acknowledge signal if the slave
address is correct.
Master sends control register address (8 bits).
Slave sends acknowledge signal.
Master sends data byte to be written to the addressed
register.
Slave sends acknowledge signal.
If master will send further data bytes the control register
address will be incremented by one after acknowledge
signal.
Write cycle ends when the master creates stop condition.
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C chip address
20186251
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Control Register Read Cycle
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<>Data from master [ ] Data from slave
Master device generates a start condition.
Master device sends slave address (7 bits) and the data
direction bit (r/w = 0).
Slave device sends acknowledge signal if the slave
address is correct.
Master sends control register address (8 bits).
Slave sends acknowledge signal.
Master device generates repeated start condition.
Master sends the slave address (7 bits) and the data
direction bit (r/w = 1).
Slave sends acknowledge signal if the slave address is
correct.
Slave sends data byte from addressed register.
If the master device sends acknowledge signal, the control
register address will be incremented by one. Slave device
sends data byte from addressed register.
Read cycle ends when the master does not generate
acknowledge signal after data byte and generates stop
condition.
Data Read
Data Write
Address Mode
<Start Condition>
<Slave Address><r/w = 0>[Ack]
<Register Addr.>[Ack]
<Repeated Start Condition>
<Slave Address><r/w = 1>[Ack]
[Register Data]<Ack or NAck>
… additional reads from subsequent
register address possible
<Stop Condition>
<Start Condition>
<Slave Address><r/w=’0’>[Ack]
<Register Addr.>[Ack]
<Register Data>[Ack]
… additional writes to subsequent
register address possible
<Stop Condition>
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