HI5760EVAL1 Intersil, HI5760EVAL1 Datasheet - Page 3

• Manufacturer Part Number: HI5760EVAL1
• Description: EVALUATION PLATFORM SOIC HI5760
• Manufacturer: Intersil

Specifications of HI5760EVAL1

• Number Of Dac's: 1
• Number Of Bits: 10
• Outputs And Type: 1, Differential
• Sampling Rate (per Second): 125M
• Data Interface: Parallel
• Settling Time: 35ns
• Dac Type: Current
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: HI5760
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Absolute Maximum Ratings
Digital Supply Voltage DV
Analog Supply Voltage AV
Grounds, ACOM TO DCOM . . . . . . . . . . . . . . . . . . -0.3V To + 0.3V
Internal Reference Output Current . . . . . . . . . . . . . . . . . . . . . . . ±50µA
Reference Input Voltage Range. . . . . . . . . . . . . . . . . . AV
Analog Output Current (I
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
Electrical Specifications
SYSTEM PERFORMANCE
Resolution
Integral Linearity Error, INL
Differential Linearity Error, DNL
Offset Error, I
Offset Drift Coefficient
Full Scale Gain Error, FSE
Full Scale Gain Drift
Full Scale Output Current, I
Output Voltage Compliance Range
DYNAMIC CHARACTERISTICS
Maximum Clock Rate, f
Output Settling Time, (t
Singlet Glitch Area (Peak Glitch)
Output Rise Time
Output Fall Time
Output Capacitance
Output Noise
1. θ
Digital Input Voltages (D9-D0, CLK, SLEEP) . . . . . . DV
JA
is measured with the component mounted on an evaluation PC board in free air.
PARAMETER
OS
SETT
CLK
OUT
DD
DD
FS
) . . . . . . . . . . . . . . . . . . . . . . . . . 24mA
)
to DCOM . . . . . . . . . . . . . . . . . +5.5V
to ACOM . . . . . . . . . . . . . . . . . +5.5V
3
AV
DD
“Best Fit” Straight Line (Note 7)
(Note 7)
(Note 7)
(Note 7)
With External Reference (Notes 2, 7)
With Internal Reference (Notes 2, 7)
With External Reference (Note 7)
With Internal Reference (Note 7)
(Note 3)
(Note 3)
0.2% (±1 LSB, equivalent to 9 Bits) (Note 7)
0.1% (±1/2 LSB, equivalent to 10 Bits) (Note 7)
R
Full Scale Step
Full Scale Step
IOUTFS = 20mA
IOUTFS = 2mA
= DV
L
= 25Ω (Note 7)
DD
= +5V, V
o
DD
DD
C to 85
REF
+ 0.3V
+ 0.3V
TEST CONDITIONS
= Internal 1.2V, IOUTFS = 20mA, T
o
C
HI5760
Thermal Information
Thermal Resistance (Typical, Note 1)
Maximum Junction Temperature
Maximum Storage Temperature Range . . . . . . . . . -65
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . .
HI5760 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150
(SOIC - Lead Tips Only)
A
= 25
o
C for All Typical Values
-0.025
MIN
-0.5
-0.3
125
-10
-10
T
10
-1
2
-
-
-
-
-
-
-
-
-
-
-
A
= -40
HI5760
±0.25
±100
TYP
±0.5
o
±50
0.1
1.0
1.5
±2
±1
20
35
10
50
30
C TO 85
5
-
-
-
-
+0.025
MAX
+0.5
1.25
+10
+10
o
+1
20
C
-
-
-
-
-
-
-
-
-
-
-
-
-
o
θ
C to 150
JA
FSR/
FSR/
FSR/
pA/√Hz
pA/√Hz
% FSR
% FSR
% FSR
UNITS
pV•s
ppm
ppm
ppm
MHz
(
135
LSB
LSB
Bits
mA
75
o
ns
ns
ns
ns
pF
V
C/W)
o
o
o
C
C
C
o
o
o
C
C
C