hi5760-6ibz Intersil Corporation, hi5760-6ibz Datasheet
hi5760-6ibz
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hi5760-6ibz Summary of contents
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... Data Sheet 10-Bit, 125/60MSPS, High Speed D/A Converter The HI5760 is a 10-bit, 125MSPS, high speed, low power, D/A converter which is implemented in an advanced CMOS process. Operating from a single +3V to +5V supply, the converter provides 20mA of full scale output current and includes edge-triggered CMOS input data latches. Low glitch energy and excellent frequency domain performance are achieved using a segmented current source architecture ...
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... Functional Block Diagram (LSB LATCH (MSB) D9 CLK AV ACOM DV DCOM HI5760 HI5760 (11-14, 25) (15) SLEEP (16) REFLO D9 (MSB) (1) (17) REFIO D8 (2) 0.1µF D7 (3) D6 (4) (18) FSADJ D5 (5) D4 (6) D3 (7) (22) IOUTA 50Ω D2 (8) D1 (9) 50Ω D0 (LSB) (10) (21) IOUTB CLK (28) ...
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... Output Noise IOUTFS = 20mA IOUTFS = 2mA 3 HI5760 Thermal Information Thermal Resistance (Typical, Note 1) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TSSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . + 0.3V Maximum Junction Temperature DD HI5760 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 + 0.3V Maximum Storage Temperature Range . . . . . . . . . -65 DD Maximum Lead Temperature (Soldering 10s .300 (SOIC - Lead Tips Only +5V Internal 1 ...
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... Electrical Specifications AV DD PARAMETER AC CHARACTERISTICS - HI5760BIB, HI5760IA - 125MHz Spurious Free Dynamic Range, f CLK SFDR Within a Window f CLK f CLK f CLK f CLK Total Harmonic Distortion (THD CLK Nyquist f CLK f CLK Spurious Free Dynamic Range, f CLK SFDR to Nyquist f CLK f CLK f CLK f CLK f CLK ...
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... It is recommended that the output current be reduced to 12mA or less to maintain optimum performance for operation below 3V not have to be equal. 9. Measured with the clock at 60MSPS and the output frequency at 10MHz. 5 HI5760 = DV = +5V Internal 1.2V, IOUTFS = 20mA REF TEST CONDITIONS for All Typical Values (Continued) A HI5760 - MIN TYP MAX UNITS 3 ...
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... OUTPUT FREQUENCY (MHz) FIGURE 3. SFDR CLOCK = 50MSPS OUT 6dBFS -12dBFS 60 55 0dBFS OUTPUT FREQUENCY (MHz) FIGURE 5. SFDR CLOCK = 125MSPS OUT 6 HI5760 76 74 -6dBFS 1.4 1.6 1 ...
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... OUT FIGURE 9. SFDR CLOCK = 100MSPS OUT -40 - TEMPERATURE ( FIGURE 11. SFDR vs TEMPERATURE, CLOCK = 100MSPS 7 HI5760 (Continued) 75 25MSPS 70 50MSPS 125MSPS - AMPLITUDE (TOTAL PEAK POWER OF COMBINED TONES) (dBFS FIGURE 8. SFDR vs AMPLITUDE OF TWO TONES, f ...
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... SFDR = 67dBc (IN A WINDOW) -60 -70 -80 -90 -100 -110 1.95MHz/DIV. 0.5 FREQUENCY (MHz) FIGURE 15. EIGHT-TONE, CLOCK = 100MSPS 0.4 0.2 0 -0.2 -0.4 0 200 400 600 CODE FIGURE 17. DIFFERENTIAL NONLINEARITY 8 HI5760 (Continued) -10 Fclk = 100MSPS f = 100MSPS CLK -20 Fout = 13.5/14.5MHz = 13.5/14.5MHz OUT COMBINED PEAK -30 MTPR = 62.9dBc SFDR = 62.9dBc -40 14dB EXTERNAL -50 -60 -70 -80 -90 50 ...
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... CLOCK = 5MSPS OUT 80 75 -6dBFS 70 -12dBFS 65 60 0dBFS OUTPUT FREQUENCY (MHz) FIGURE 22. SFDR CLOCK = 50MSPS OUT 9 HI5760 (Continued) 160 155 150 145 140 135 130 125 120 115 110 105 CLOCK RATE (MSPS) CLK / 80 -6dBFS 75 ...
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... AMPLITUDE (dBFS) FIGURE 26. SFDR vs AMPLITUDE (MA) OUT FIGURE 28. SFDR CLOCK = 100MSPS OUT 10 HI5760 (Continued FIGURE 25. SFDR vs AMPLITUDE 25MSPS 70 65 50MSPS 60 100MSPS ...
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... ANALYZER ATTENUATION -70 -80 -90 -100 -110 0 5MHz/DIV. FREQUENCY (MHz) FIGURE 32. TWO-TONE, CLOCK = 100MSPS -20 -30 f -40 -50 -60 -70 -80 -90 -100 -110 0.5 1.95MHz/DIV. FREQUENCY (MHz) FIGURE 34. EIGHT-TONE, CLOCK = 100MSPS 11 HI5760 (Continued) -10 -20 2.5MHz -30 10.1MHz -40 -50 -60 -70 -80 40.4MHz -90 -100 -110 100MSPS CLK f = 13.5/14.5MHz ...
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... Typical Performance Curves, 3V Power Supply 0.4 0.2 0 -0.2 -0.4 0 200 400 600 CODE FIGURE 36. DIFFERENTIAL NONLINEARITY FIGURE 38. POWER vs CLOCK RATE HI5760 (Continued) 0.4 0.2 0 -0.2 -0.4 800 1000 CLOCK RATE (MSPS) f CLK / OUT 200 400 600 800 CODE FIGURE 37. INTEGRAL NONLINEARITY ...
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... OUT t SETT t PD FIGURE 39. OUTPUT SETTLING TIME DIAGRAM CLK t SU D9-D0 I OUT t PD FIGURE 41. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM 13 HI5760 50 LSB ERROR BAND 2 FIGURE 40. PEAK GLITCH AREA (SINGLET) MEASUREMENT t t PW1 PW2 HLD ...
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... Tmin or Tmax. The units are ppm per degree C. Detailed Description The HI5760 is a 10-bit, current out, CMOS, digital to analog converter. Its maximum update rate is 125MSPS and can be powered by either single or dual power supplies in the recommended range of +3V to +5V. It consumes less than 165mW of power when using a +5V supply with the data switching at 100MSPS ...
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... Digital Inputs and Termination The HI5760 digital inputs are guaranteed to CMOS levels. However, TTL compatibility can be achieved by lowering the supply voltage to 3V due to the digital threshold of the input buffer being approximately half of the supply voltage. The internal register is updated on the rising edge of the clock. ...
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... CLK 16 HI5760 PIN DESCRIPTION Digital Data Bit 9 (Most Significant Bit) through Digital Data Bit 0, (Least Significant Bit). No Connect. Recommend ground. Control Pin for Power-Down mode. Sleep Mode is active high; Connect to ground for Normal Mode. Sleep pin has internal 20µA active pulldown current. ...
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... The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimen- sions are not necessarily exact. 17 HI5760 M28.3 (JEDEC MS-013-AE ISSUE C) 28 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE M B ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 18 HI5760 M28.173 28 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE ...