DM300023 Microchip Technology, DM300023 Datasheet - Page 5

• Manufacturer Part Number: DM300023
• Description: KIT DEMO DSPICDEM SMPS BUCK
• Manufacturer: Microchip Technology
• Series: dsPIC™r

Specifications of DM300023

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 2, Non-Isolated
• Voltage - Input: 7 ~ 15V
• Regulator Topology: Buck
• Board Type: Fully Populated
• Utilized Ic / Part: dsPIC30F2020
• Processor To Be Evaluated: dsPIC30F202x/1010
• Interface Type: RS-232
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Voltage - Output: -
• Power - Output: -
• Frequency - Switching: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5. Module: ADC Interrupts
6. Module: ADC Module: Shared Sample
© 2008 Microchip Technology Inc.
The dsPIC30F1010/202X data sheet specifies that
each ADC pin pair has its own interrupt vector.
These
dsPIC30F1010/202X Rev. A1 devices.
Work around
Each ADC pin pair can be configured to initiate a
global ADC interrupt by setting the corresponding
IRQENx bit in the ADCPCx register. The ADBASE
register can be used to create a jump table in the
global ADC interrupt which will execute the
appropriate ADC service routine for a particular
ADC pin pair. There is an ADBASE register code
example in the dsPIC30F1010/202X data sheet
which illustrates using the ADBASE register in this
way.
The ADC inputs that do not have a dedicated
sample and hold circuit will yield inaccurate
conversion results unless the work around is
implemented. The channels included are AN1,
AN3, AN5, AN7, AN8, AN9, AN10 and AN11
(depending on package). This applies to AN4 and
AN6, and to the dsPIC30F1010.
Work around
In the ADCON register, configure the ADC with
Order = 0 and SEQSAMP = 1. This configuration
allows for accurate conversion of the analog
channels which use the shared sample and hold
circuit. The exception to this is the RB7 pin and all
multiplexed functions (see Module 8).
interrupts
and Hold Circuit
do
not
work
on
the
7. Module: ADC Module: Global Software
dsPIC30F1010/202X
In order to perform multiple analog-to-digital
conversions using the global software trigger, the
PxRDY bits in the ADSTAT register must be
cleared. The data sheet indicates that the user can
configure the ADC pin pairs to perform a
conversion when the GSWTRG bit in the ADCON
register is set. When the conversion is available,
the user must then clear the GSWTRG bit and set
it again to perform another conversion. Contrary to
what the data sheet indicates, this will not initiate
another conversion unless the PxRDY bits are
cleared. Clearing the PxRDY bits automatically
clears the GSWTRG bit.
This only applies to a polling based approach. If an
interrupt based approach is used, the user is
required to clear the PxRDY bits in the ADC
Interrupt Service Routine (ISR).
Work around
To manually trigger ADC conversions using the
global software trigger (polling based only), follow
the sequence given below:
1. Set the GSWTRG bit in ADCON to initiate a
2. Check the PxRDY bits to determine when the
3. Clear the PxRDY bits. The GSWTRG bit will be
4. Repeat steps 1 to 3 to perform additional
Alternatively, the individual software trigger can be
selected by setting the TRGSRCx<5:0> bits in the
ADCPCx register equal to 0x01. Instead of using
the global software trigger, the individual software
trigger (ADCPCx<SWTRGx>) bits can be used to
trigger a conversion on a given analog pin pair. In
a bit polling approach, the PENDx in the ADCPCx
register should be used to determine when a
conversion is completed. In an interrupt based
approach, the PxRDY bits get set when the
conversion is complete. This bit must be cleared in
the ADC Interrupt Service Routine in order to
enable future interrupts.
conversion on channels which have the trigger
source as the global software trigger (via the
TRGSRCx<5:0> bits in the ADCPCx
registers).
conversion(s) is completed.
cleared as a result of this operation.
conversions.
Trigger
DS80290J-page 5