ADC08D1500DEV/NOPB National Semiconductor, ADC08D1500DEV/NOPB Datasheet - Page 21

• Manufacturer Part Number: ADC08D1500DEV/NOPB
• Description: BOARD DEV FOR ADC08D1500
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08D1500DEV/NOPB

• Mfg Application Notes: Clocking High-Speed A/D Converters AppNote
• Number Of Adc's: 2
• Number Of Bits: 8
• Sampling Rate (per Second): 1.5G
• Data Interface: Serial
• Inputs Per Adc: 1 Differential
• Input Range: 870 mVpp
• Power (typ) @ Conditions: 1.8W @ 1.5GSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08D1500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08D1500DEV

10.2 Expansion Header
A 72 pin Future Bus Expansion Header is provided on the rear panel to allow easy connection to a third
party microprocessor board to allow for the reading and analysis of the data captured by the FPGA.
The signals connector to this expansion bus will be as follows
PIN
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
C15
C16
C17
C18
The Data busses on this header can be configured as follows
All control signals on pins A1 to A15 will be at LVCMOS 3.3V levels.
•
•
Two 8 bit busses with LVDS differential signaling, plus two LVDS strobes
Four 8 bit busses with LVCMOS (3.3V IO) signaling plus four CMOS strobes
DESCRIPTION
I2C - SDA
I2C - SCL
SSP - SERIAL DATA
SSP - SERIAL CLOCK
FPGA RESET
READ FIFO
WRITE FIFO
FIFO FULL
FIFO EMPTY
ADC DCLK RESET
FPGA CONF DONE
FPGA JTAG – TMS
FPGA JTAG - TCK
FPGA JTAG – TDI
FPGA JTAG – TDO
notSHUTDOWN
3.3V SUPPLY
12V SUPPLY
DATA BUS A P0 (LVDS or CMOS)
DATA BUS A P1 (LVDS or CMOS)
DATA BUS A P2 (LVDS or CMOS)
DATA BUS A P3 (LVDS or CMOS)
DATA BUS A P4 (LVDS or CMOS)
DATA BUS A P5 (LVDS or CMOS)
DATA BUS A P6 (LVDS or CMOS)
DATA BUS A P7 (LVDS or CMOS)
INPUT STROBE P
DATA BUS B P0 (LVDS or CMOS)
DATA BUS B P1 (LVDS or CMOS)
DATA BUS B P2 (LVDS or CMOS)
DATA BUS B P3 (LVDS or CMOS)
DATA BUS B P4 (LVDS or CMOS)
DATA BUS B P5 (LVDS or CMOS)
DATA BUS B P6 (LVDS or CMOS)
DATA BUS B P7 (LVDS or CMOS)
OUTPUT STROBE P
PIN
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
DATA BUS A N0 (LVDS or CMOS)
DATA BUS A N1 (LVDS or CMOS)
DATA BUS A N2 (LVDS or CMOS)
DATA BUS A N3 (LVDS or CMOS)
DATA BUS A N4 (LVDS or CMOS)
DATA BUS A N5 (LVDS or CMOS)
DATA BUS A N6 (LVDS or CMOS)
DATA BUS A N7 (LVDS or CMOS)
INPUT STROBE N
DATA BUS B N0 (LVDS or CMOS)
DATA BUS B N1 (LVDS or CMOS)
DATA BUS B N2 (LVDS or CMOS)
DATA BUS B N3 (LVDS or CMOS)
DATA BUS B N4 (LVDS or CMOS)
DATA BUS B N5 (LVDS or CMOS)
DATA BUS B N6 (LVDS or CMOS)
DATA BUS B N7 (LVDS or CMOS)
OUTPUT STROBE N
DESCRIPTION
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
GROUND
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