EVAL-AD7612CB Analog Devices Inc, EVAL-AD7612CB Datasheet - Page 17

• Manufacturer Part Number: EVAL-AD7612CB
• Description: BOARD EVALUATION AD7612
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7612CB

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 750k
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Single Ended
• Input Range: ±5 V, ±10 V
• Power (typ) @ Conditions: 205mW @ 750kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7612
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

THEORY OF OPERATION
OVERVIEW
The AD7612 is a very fast, low power, precise, 16-bit analog-to-
digital converter (ADC) using successive approximation capacitive
digital-to-analog (CDAC) architecture.
The AD7612 can be configured at any time for one of four input
ranges and conversion mode with inputs in parallel and serial
hardware modes or by a dedicated write only, SPI-compatible
interface via a configuration register in serial software mode.
The AD7612 uses Analog Device’s patented iCMOS high voltage
process to accommodate 0 to 5 V, 0 to 10 V, ±5 V, and ±10 V
input ranges without the use of conventional thin films. Only
one acquisition cycle, t
correct configuration. Resetting or power cycling is not
required for reconfiguring the ADC.
The AD7612 features different modes to optimize performance
according to the applications. It is capable of converting 750,000
samples per second (750 kSPS) in warp mode, 600 kSPS in normal
mode, and 500 kSPS in impulse mode.
The AD7612 provides the user with an on-chip track-and-hold,
successive approximation ADC that does not exhibit any pipe-
line or latency, making it ideal for multiple multiplexed channel
applications.
For unipolar input ranges, the AD7612 typically requires three
supplies; VCC, AVDD (which can supply DVDD), and OVDD
which can be interfaced to either 5 V, 3.3 V, or 2.5 V digital logic.
For bipolar input ranges, the AD7612 requires the use of the
additional VEE supply.
The device is housed in Pb-free, 48-lead LQFP or tiny LFCSP
7 mm × 7 mm packages that combine space savings with flexi-
bility. In addition, the AD7612 can be configured as either a
parallel or serial SPI-compatible interface.
REFGND
8
, is required for the inputs to latch to the
REF
IN+
IN–
32,768C
16,384C
MSB
4C
Figure 25. ADC Simplified Schematic
2C
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65,536C
C
C
CONVERTER OPERATION
The AD7612 is a successive approximation ADC based on a
charge redistribution DAC. Figure 25 shows the simplified
schematic of the ADC. The CDAC consists of two identical
arrays of 16 binary weighted capacitors, which are connected
to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to AGND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on IN+ and IN− inputs. A conversion
phase is initiated once the acquisition phase is complete and the
CNVST input goes low. When the conversion phase begins, SW+
and SW− are opened first. The two capacitor arrays are then
disconnected from the inputs and connected to the REFGND
input. Therefore, the differential voltage between the inputs
(IN+ and IN−) captured at the end of the acquisition phase is
applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between REFGND and REF, the comparator input varies
by binary weighted voltage steps (V
65536). The control logic toggles these switches, starting with
the MSB first, in order to bring the comparator back into a
balanced condition.
After the completion of this process, the control logic generates
the ADC output code and brings the BUSY output low.
LSB
SW
SW
COMP
A
B
SWITCHES
CONTROL
CONTROL
CNVST
LOGIC
OUTPUT
CODE
BUSY
REF
/2, V
REF
/4 through V
AD7612
REF
/