EVB9221-MINI SMSC, EVB9221-MINI Datasheet - Page 46
![EVALUATION BOARD LAN9221-ABZJ](/photos/9/10/91030/evb9221-mini_sml.jpg)
EVB9221-MINI
Manufacturer Part Number
EVB9221-MINI
Description
EVALUATION BOARD LAN9221-ABZJ
Manufacturer
SMSC
Datasheet
1.LAN9221-ABZJ.pdf
(152 pages)
Specifications of EVB9221-MINI
Main Purpose
Interface, Ethernet Controller (PHY and MAC)
Embedded
No
Utilized Ic / Part
LAN9221
Primary Attributes
1 Port, 100BASE-TX/10BASE-T
Secondary Attributes
16-Bit, HP Auto-MDIX, Full and Half Duplex Support, 32-Bit CRC
Processor To Be Evaluated
LAN9221
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1074
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Revision 2.7 (03-15-10)
MAC and Host
Internal Clock
Management
MAC Power
Interface
BLOCK
Device
PHY
Note 3.16 The PME interrupt status bit on the INT_STS register (PME_INT) is set regardless of the
A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return the
LAN9221/LAN9221i to the D0 state and will reset the PM_MODE field to the D0 state. As noted above,
the host is required to check the READY bit and verify that it is set before attempting any other reads
or writes of the device. Before the LAN9221/LAN9221i is fully awake from this state the EDPWRDOWN
bit in register 17 of the PHY must be cleared in order to wake the PHY. Do not attempt to clear the
EDPWRDOWN bit until the READY bit is set. After clearing the EDPWRDOWN bit the
LAN9221/LAN9221i is ready to resume normal operation. At this time the WUPS field can be cleared.
setting of PME_EN.
(NORMAL OPERATION)
Full ON
Full ON
Full ON
Full ON
Table 3.10 Power Management States
D0
KEY
CLOCK ON
BLOCK DISABLED – CLOCK ON
FULL OFF
DATASHEET
RX Power Mgmt. Block
46
High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Full ON
Full ON
(WOL)
OFF
D1
On
Energy Detect Power-Down
(ENERGY DETECT)
SMSC LAN9221/LAN9221i
OFF
OFF
OFF
D2
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