EVB9221-MINI SMSC, EVB9221-MINI Datasheet - Page 43
![EVALUATION BOARD LAN9221-ABZJ](/photos/9/10/91030/evb9221-mini_sml.jpg)
EVB9221-MINI
Manufacturer Part Number
EVB9221-MINI
Description
EVALUATION BOARD LAN9221-ABZJ
Manufacturer
SMSC
Datasheet
1.LAN9221-ABZJ.pdf
(152 pages)
Specifications of EVB9221-MINI
Main Purpose
Interface, Ethernet Controller (PHY and MAC)
Embedded
No
Utilized Ic / Part
LAN9221
Primary Attributes
1 Port, 100BASE-TX/10BASE-T
Secondary Attributes
16-Bit, HP Auto-MDIX, Full and Half Duplex Support, 32-Bit CRC
Processor To Be Evaluated
LAN9221
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1074
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High-Performance 16-bit Non-PCI 10/100 Ethernet Controller with Variable Voltage I/O
Datasheet
SMSC LAN9221/LAN9221i
EEDIO (OUTPUT)
EEDIO (OUTPUT)
EEDIO (INPUT)
EEDIO (INPUT)
EEDIO (OUTPUT)
EEDIO (INPUT)
EECLK
EECLK
EECS
EECS
READ (Read Location): This command will cause a read of the EEPROM location pointed to by EPC
Address (EPC_ADDR). The result of the read is available in the E2P_DATA register.
WRITE (Write Location): If erase/write operations are enabled in the EEPROM, this command will
cause the contents of the E2P_DATA register to be written to the EEPROM location selected by the
EPC Address field (EPC_ADDR). The EPC_TO bit is set if the EEPROM does not respond within
30ms.
WRAL (Write All): If erase/write operations are enabled in the EEPROM, this command will cause the
contents of the E2P_DATA register to be written to every EEPROM memory location. The EPC_TO bit
is set if the EEPROM does not respond within 30ms.
Table 3.9, "Required EECLK
each EEPROM operation.
EECLK
EECS
1
1
0
0
1
0
Figure 3.10 EEPROM WRITE Cycle
1
Figure 3.11 EEPROM WRAL Cycle
Figure 3.9 EEPROM READ Cycle
1
0
Cycles", shown below, shows the number of EECLK cycles required for
A6
1
0
DATASHEET
A6
43
A0
D7
D7
A0
D7
D0
D0
t
t
CSL
CSL
D0
Revision 2.7 (03-15-10)
t
CSL
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