SI5315-EVB Silicon Laboratories Inc, SI5315-EVB Datasheet

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... PON OLT/ONU  Description The Si5315 is a jitter-attenuating clock multiplier for Gb and 10G Synchronous Ethernet, SONET/SDH, and PDH (T1/E1) applications. The Si5315 accepts dual clock inputs ranging from 8 kHz to 644.53 MHz and generates two equal frequency- multiplied clock outputs ranging from 8 kHz to 644.53 MHz. The input clock frequency and clock multiplication ratio are selectable from a table of popular SyncE and T1/E1 rates ...

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... Si5315 2 Rev. 0.26 ...

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... Crystal/Reference Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 7. Power Supply Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 8. Typical Phase Noise Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 8.1. Example: 10G LAN SyncE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9. Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 10. Pin Descriptions: Si5315 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 11. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 12. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 13. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 14. Si5315 Device Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Document Change List: ...

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... CKN Single-ended Input Voltage Swing Differential Input Voltage Swing Notes: 1. Refers to Si5315A speed grade. 2. Refers to Si5315B speed grade. 3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 12 – ºC) A Test Condition 3.3 V nominal 2.5 V nominal 1.8 V nominal = – ...

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... DD Output Voltage Low CKO Output Voltage High CKO Notes: 1. Refers to Si5315A speed grade. 2. Refers to Si5315B speed grade. 3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 12. = – ºC) A Test Condition LVPECL 100  load ...

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... Input Resistance XA Input Voltage Level Limits XA Input Voltage Swing XA Notes: 1. Refers to Si5315A speed grade. 2. Refers to Si5315B speed grade. 3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 12 – ºC) A Test Condition CMOS IO Driving into CKO ...

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... Differential Input Voltage XA/XB Level Limits Input Voltage Swing XA VPP Notes: 1. Refers to Si5315A speed grade. 2. Refers to Si5315B speed grade. 3. This is the amount of leakage that the 3L inputs can tolerate from an external driver. See Figure 3 on page 12. = – ºC) A Test Condition XTAL/CLOCK = M RIN ...

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... LOSn Trigger Window LOSX Trigger Window Time to Clear LOS Alarm Time to Declare LOL after LOS Time to Clear LOL after LOS Cleared t Notes: 1. Assumes N3 does not equal CKN 2. Refers to Si5315A speed grade. 3. Refers to Si5315B speed grade – ºC) A Symbol Test Condition CKN F ...

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... Holdover Initial Frequency Error Holdover Frequency Stability vs. Power Supply Holdover Frequency Deviation vs. Temperature Spurious Noise Notes: 1. Assumes N3 does not equal CKN 2. Refers to Si5315A speed grade. 3. Refers to Si5315B speed grade. = – ºC) A Symbol Test Condition RST with valid CKIN to  t LOCKHW LOL ...

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... BWSEL [1:0] loop bandwidth settings provided in Table 7 on page 20 MHz fundamental mode crystal used as XA/XB input 2 ° Si5315A test condition 19.44 MHz (20–80%), LVPECL clock output. 6. Si5315B test condition: f =19.44 MHz 80%), LVPECL clock output. Table 5. Thermal Characteristics (V = 1.8 ±5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol  Thermal Resistance ...

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... V ICM OCM SIGNAL – (SIGNAL +) – (SIGNAL – ICM OCM SIGNAL + SIGNAL – Figure 1. CKIN Voltage Characteristics DOUT, CLOUT Figure 2. Rise/Fall Time Characteristics Single-Ended ISE OSE Peak-to-Peak Voltage Differential V ,V Peak-to-Peak Voltage (SIGNAL+) – (SIGNAL– Rev. 0.26 Si5315 80% 20% 11 ...

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... Input Voltage High Input Low Current Input Mid Current Input High Current Note: The above currents are the amount of leakage that the 3L inputs can tolerate from an external driver Si5315 75 k I imm 75 k Figure 3. Three Level Input Pins Symbol Min Vill — ...

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... If a pin is left open (no connect), no resistors are needed.  Si5315 18 k I imm 18 k Figure 4. Three Level Input Pins Symbol Min Iill –30 µA Iimm –11 µA Iihh — Rev. 0.26 Si5315 DD 75 k 75 k Max — –11 µA –30 µA 13 ...

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... Si5315 Table 6. Absolute Maximum Ratings Parameter DC Supply Voltage LVCMOS Input Voltage Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pF, 1.5 k); All pins except CKIN+/CKIN– ESD MM Tolerance; All pins except CKIN+/CKIN– ESD HBM Tolerance (100 pF, 1.5 k); CKIN+/CKIN– ...

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... MHz. For ease of use, the Si5315 is pin controlled to enable simple device configuration of frequency plans, PLL loop bandwidth, and input clock selection. The DSPLL locks to one of two input reference clocks and provides over 200 frequency translations to synchronize output clocks for Ethernet, SONET/SDH, and PDH line cards ...

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... PLL. The lock detect algorithm works by continuously monitoring the phase of the input clock in relation to the phase of the feedback clock. The Si5315 provides a holdover capability that allows the device to continue generation of a stable output clock when the selected input reference is lost. ...

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... The DSPLL technology used in the Si5315 provides tightly controlled jitter transfer curves because the PLL gain parameters are determined largely by digital circuits which do not vary over supply voltage, process, and temperature system application, a well-controlled transfer curve minimizes the output clock jitter variation from board to board and provides more consistent system level jitter performance ...

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... In either case, the device accepts a wide margin in absolute frequency of the reference input. (See 4.5. "Holdover Mode" on page 35.) In holdover, the Si5315's output clock stability matches the reference supplied on the XA/XB pins. The external crystal or reference clock must be selected based on the stability requirements of the application if holdover is a key requirement ...

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... Frequency Plan Tables For ease of use, the Si5315 is pin controlled to enable simple device configuration of the frequency plan and PLL loop bandwidth via a predefined look up table. The DSPLL has been optimized for each frequency multiplication and PLL loop bandwidth provided in Table 7 on page 20. ...

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... Si5315 20 Rev. 0.26 ...

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... Rev. 0.26 Si5315 21 ...

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... Si5315 22 Rev. 0.26 ...

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... Rev. 0.26 Si5315 23 ...

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... Si5315 24 Rev. 0.26 ...

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... Rev. 0.26 Si5315 25 ...

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... Si5315 26 Rev. 0.26 ...

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... Rev. 0.26 Si5315 27 ...

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... Si5315 28 Rev. 0.26 ...

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... Rev. 0.26 Si5315 29 ...

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... Si5315 4.2. PLL Self-Calibration An internal self-calibration (ICAL) is performed before operation to optimize loop parameters and jitter performance. While the self-calibration is being performed, the DSPLL is being internally controlled by the self- calibration state machine. The LOL alarm will be active during ICAL. The self-calibration time t Table 3, “ ...

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... The Maximum Time Interval Error (MTIE) and maximum slope for clock output phase transients during clock switching are given in (Table 3, “AC Characteristics”). These values fall significantly below the limits specified in the ITU-T G.8262, Telcordia GR-1244-CORE, and GR-253-CORE requirements. Table 8. Si5315 Pins and Reset Must Reset after Changing Yes Yes ...

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... Manual Clock Selection Manual control of input clock selection is chosen via the CS_CA pin according to Table 9 and Table 10. Table 9. Automatic/Manual Clock Selection AUTOSEL Table 10. Manual Input Clock Selection, AUTOSEL = L CS_CA Clock Selection Mode Manual Automatic non-revertive Automatic revertive Si5315 AUTOSEL = L CKIN1 CKIN2 Rev. 0.26 ...

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... Non-revertive (AUTOSEL = M): The active clock does not change until there is an alarm on the active clock. The device will then select the highest priority CKINn that is valid. Once in holdover, the device will switch to the first CKINn that becomes valid. Active Clock CKIN1 CKIN2 Priority Input Clocks 1 CKIN1 2 CKIN2 3 Holdover Rev. 0.26 Si5315 33 ...

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... Si5315 4.4. Alarms Summary alarms are available to indicate the overall status of the input signals. Alarm outputs stay high until all the alarm conditions for that alarm output are cleared. 4.4.1. Loss-of-Signal The device has loss-of-signal circuitry that continuously monitors CKINn for missing pulses. The LOS circuitry generates an internal LOSn_INT output signal that is processed with other alarms to generate LOS1 and LOS2 ...

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... The clock transition from holdover to the returned input clock includes "phase buildout" to absorb the phase difference between the holdover clock phase and the input clock phase. See Table 3, “AC Characteristics” for specifications. Rev. 0.26 Si5315 35 ...

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... Si5315 4.6. PLL Bypass Mode The Si5315 supports a PLL bypass mode in which the selected input clock is fed directly to both enabled output buffers, bypassing the DSPLL. Internally, the bypass path is implemented with high-speed differential signaling; however, this path is not a low jitter path and will see significantly higher jitter on CKOUT. In PLL bypass mode, the input and output clocks will be at the same frequency ...

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... High-Speed I/O 5.1. Input Clock Buffers The Si5315 provides differential inputs for the CKINn clock inputs. These inputs are internally biased to a common mode voltage [see Table 2, “DC Characteristics”] and can be driven by either a single-ended or differential source. Figure 10 through Figure 13 show typical interface circuits for LVPECL, CML, LVDS, or CMOS input clocks. Note that the jitter generation improves for higher levels on CKINn (within the limits in Table 3, “ ...

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... Si5315 CML/ LVDS Driver Figure 12. CML/LVDS Termination (1.8, 2.5, 3 CMOS Driver Figure 13. CMOS Termination (1.8, 2.5, 3 Si5315 C   100 40 k Si5315  CKIN +   CKIN 0.1 uF Rev. 0.26 CKIN +  300 ± V ICM _ CKIN  300 ± V ICM ...

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... Output Clock Drivers The Si5315 has a flexible output driver structure that can drive a variety of loads, including LVPECL, LVDS, CML, and CMOS formats. The signal format is selected for both CKOUT1 and CKOUT2 outputs using the SFOUT [1:0] pins. This modifies the output common mode and differential signal swing. See Table 2, “DC Characteristics” for output driver specifications ...

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... Si5315 SFOUT[1: (Output disable) Output from DSPLL Figure 16. Disable CKOUTn Structure The SFOUT [1:0] pins can also be used to disable both outputs. Disabling the output puts the CKOUTn+ and CKOUTn– pins in a high-impedance state relative to V connected to each other through a 200  on-chip resistance (differential impedance of 200 ). The maximum amount of internal circuitry is powered down, minimizing power consumption and noise generation. Recovery from the disable mode requires additional time as specified in Table 3, “ ...

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... Figure 19. Differential External Reference Clock Input Example 3.3 V 150  130  0.1  150  0.1 F 0.01 F XA 0.01   0.1 µF 0.01 F XA  100 XB 0.01 F Rev. 0.26 Si5315 Si5315 10 k 0.6 V 1.2 V Si5315 k 0.6 V Si5315 1 k 10 k 0 ...

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... Mtron Note: While these crystals meet the preceding criteria according to their data sheets, Silicon Laboratories, Inc. does not guarantee operation with the Si5315, nor does Silicon Laboratories endorse one supplier of crystals over another. Contact Silicon Labs for details and a current list of crystal vendors and recommended part numbers ...

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... A typical reference input-to-output jitter transfer function is shown in Figure 20 -10 -15 -20 -25 - Figure 20. Typical XA/XB Reference Jitter Transfer Function Jitter Transfer XA/XB Reference to CKOUT 40 MHz Clock on XA/XB, XTAL/Clock=M 100 1000 10000 Jitter Frequency (Hz) Rev. 0.26 Si5315 100000 1000000 43 ...

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... Internal core circuitry is driven from the output of this regulator while I/O circuitry uses the external supply voltage directly. Table 3, “AC Characteristics” gives the sensitivity of the on-chip oscillator to changes in the supply voltage. Refer to the Si5315 evaluation board for an example. The center ground pad under the device must be electrically and thermally connected to the ground plane. ...

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... Si5315 operates at 3.3 V with an ac coupled differential PECL output and an ac coupled differential sine wave input from the RF generator at 0 dBm. Note that, as with any PLL, the output jitter that is below the loop BW is caused by the jitter at the input clock, not the Si5315. Except as noted, loop BWs 240 Hz were in use. 8.1. Example: 10G LAN SyncE 0 ‐ ...

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... Clock Output 2 Disable/ Bypass Mode Control 15 k Reset Notes: 1. Assumes differential LVPECL termination (3 clock inputs. 2. Denotes tri-level input pins with states designated as L (ground Assumes manual input clock selection. Figure 23. Si5315 Typical Application Circuit µ 0.1 µF 3 Ferrite ...

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... Active low input that performs external hardware reset of device. Resets all internal logic to a known state. Clock out- puts are tristated during reset. After rising edge of RST sig- nal, the Si5315 will perform an internal self-calibration when a valid input signal is present. This pin has a weak pull-up. ...

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... Si5315 Table 18. Si5315 Pin Descriptions (Continued) Pin # Pin Name I GND GND 15,19, 20,31 9 AUTOSEL I 11 XTAL/CLOCK I 12 CKIN2 CKIN2– 48 Signal Level Supply Supply. The device operates from a 1.8, 2.5, or 3.3 V supply. Bypass capacitors should be associated with the following V 5 0.1 µ ...

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... Table 18. Si5315 Pin Descriptions (Continued) Pin # Pin Name I/O 14 DBL2_BY I 16 CKIN1 CKIN1– 18 LOL O 21 CS_CA I/O 23 BWSEL1 I 22 BWSEL0 Signal Level 3-Level Output 2 Disable/Bypass Mode Control. Controls enable of CKOUT2 divider/output buffer path and PLL bypass mode CKOUT2 enabled M = CKOUT2 disabled ...

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... Si5315 Table 18. Si5315 Pin Descriptions (Continued) Pin # Pin Name I/O 27 FRQSEL3 I 26 FRQSEL2 25 FRQSEL1 24 FRQSEL0 29 CKOUT1– CKOUT1+ 33 SFOUT0 I 30 SFOUT1 34 CKOUT2– CKOUT2 — GND GND GND PAD 50 Signal Level 3-Level Frequency Select. Three level inputs that select the input clock and clock multi- plication ratio, depending on the FRQTBL setting ...

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... Table 19. Si5315 Pull-up/Pull-down Pin # Si5315 Pull? 1 RST U 2 FRQTBL AUTOSEL XTAL CLOCK 14 DBL2_BY CS_CA BWSEL0 BWSEL1 FRQSEL0 FRQSEL1 FRQSEL2 FRQSEL3 SFOUT1 SFOUT0 U, D Rev. 0.26 Si5315 51 ...

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... Ordering Guide Ordering Part Number Output Clock Freq Range Si5315A-C-GM 8 kHz–644.53 MHz Si5315B-C-GM 8 kHz–125 MHz Si5315-EVB 8 kHz–644.53 MHz Add the end of the device to denote tape and reel options (i.e., Si5315A-C-GMR). Note: Table 20. Any-rate Precision Clock Product Selection Guide Part ...

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... Package Outline: 36-Pin QFN Figure 24 illustrates the package details for the Si5315. Table 21 lists the values for the dimensions shown in the illustration. Figure 24. 36-Pin Quad Flat No-Lead (QFN) Symbol Millimeters Min Nom A 0.80 0.85 A1 0.00 0.02 b 0.18 0.25 D 6.00 BSC D2 3.95 4 ...

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... Si5315 13. Recommended PCB Layout Figure 26. Ground Pad Recommended Layout 54 Figure 25. PCB Land Pattern Diagram Rev. 0.26 ...

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... The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. MIN MAX 0.50 BSC. 5.42 REF. 5.42 REF. 4.00 4.20 4.00 4.20 4.53 — 4.53 — — 0.28 0.89 REF. — 6.31 — 6.31 Rev. 0.26 Si5315 55 ...

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... Si5315 14. Si5315 Device Top Mark Speed Code Product Revision G: Temperature Range – °C M: Package: QFN YY: Year WW: Week R: Die Rev F: Internal SiLabs Code X: Lot Code Rev. 0.26 ...

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... Supply Filtering” Updated Typical phase noise plot and RMS jitter  table in Section 8. "Typical Phase Noise Plots” Revision 0.25 to Revision 0.26 Corrected Section 11. "Ordering Guide” Output  Clock Frequency Range for Si5315B-C- kHz–125 Mhz. : Rev. 0.26 Si5315 57 ...

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... Si5315 C I ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...