LMX2485E EVAL National Semiconductor, LMX2485E EVAL Datasheet - Page 5

• Manufacturer Part Number: LMX2485E EVAL
• Description: BOARD EVALUATION LMX2485E
• Manufacturer: National Semiconductor
• Series: PLLatinum™r

Specifications of LMX2485E EVAL

• Main Purpose: Timing, Frequency Synthesizer
• Utilized Ic / Part: LMX2485E
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

PHASE NOISE
L
L
DIGITAL INTERFACE (DATA, CLK, LE, ENOSC, CE, Ftest/LD, FLoutRF)
V
V
I
I
V
V
MICROWIRE INTERFACE TIMING
t
t
t
t
t
t
IH
IL
CS
CH
CWH
CWL
ES
EW
F1Hz
F1Hz
IH
IL
OH
OL
Note 3: A slew rate of at least 100 V/uS is recommended for frequencies below 500 MHz for optimal performance.
Note 4: For Phase Detector Frequencies above 20 MHz, Cycle Slip Reduction (CSR) may be required. Legal divide ratios are also required.
Note 5: Refer to table in Section 2.4.2 RF_CPG -- RF PLL Charge Pump Gain for complete listing of charge pump currents.
Note 6: In order to measure the in-band spur, the fractional word is chosen such that when reduced to lowest terms, the fractional numerator is one. The spur
offset frequency is chosen to be the comparison frequency divided by the reduced fractional denominator. The loop bandwidth must be sufficiently wide to negate
the impact of the loop filter. Measurement conditions are: Spur Offset Frequency = 10 kHz, Loop Bandwidth = 100 kHz, Fraction = 1/2000, Comparison Frequency
= 20 MHz, RF_CPG = 7, DITH = 0, and a 4th Order Modulator (FM = 0). These are relatively consistent over tuning range.
Note 7: Normalized Phase Noise Contribution is defined as: L
measured at an offset frequency, f, in a 1 Hz Bandwidth. The offset frequency, f, must be chosen sufficiently smaller than the PLL loop bandwidth, yet large
enough to avoid substantial phase noise contribution from the reference source. Measurement conditions are: Offset Frequency = 11 kHz, Loop Bandwidth = 100
kHz for RF_CPG = 7, Fraction = 1/2000, Comparison Frequency = 20 MHz, FM = 0, DITH = 0.
MICROWIRE INPUT TIMING DIAGRAM
Symbol
RF
IF
RF Synthesizer
Normalized Phase Noise
Contribution (Note 7)
IF Synthesizer
Normalized Phase Noise
Contribution
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current V
Low-Level Input Current
High-Level Output
Voltage
Low-Level Output
Voltage
Data to Clock Set Up
Time
Data to Clock Hold Time See MICROWIRE Input Timing
Clock Pulse Width High
Clock Pulse Width Low
Clock to Load Enable Set
Up Time
Load Enable Pulse Width See MICROWIRE Input Timing
Parameter
RF_CPG = 0
RF_CPG = 1
RF_CPG = 3
RF_CPG = 7
RF_CPG = 15
V
I
I
See MICROWIRE Input Timing
See MICROWIRE Input Timing
See MICROWIRE Input Timing
See MICROWIRE Input Timing
OH
OL
IH
IL
= 500 µA
= 0 V
= V
= -500 µA
N
CC
(f) = L(f) – 20log(N) – 10log(f
Conditions
5
COMP
) where L(f) is defined as the single side band phase noise
V
CC
Min
-1.0
-1.0
1.6
25
25
25
25
25
8
-0.4
Value
-202
-202
-206
-208
-210
-209
Typ
Max
V
0.4
1.0
1.0
0.4
CC
20087775
www.national.com
dBc/Hz
dBc/Hz
Units
µA
µA
ns
ns
ns
ns
ns
ns
V
V
V
V