LMX2485E EVAL National Semiconductor, LMX2485E EVAL Datasheet - Page 21

• Manufacturer Part Number: LMX2485E EVAL
• Description: BOARD EVALUATION LMX2485E
• Manufacturer: National Semiconductor
• Series: PLLatinum™r

Specifications of LMX2485E EVAL

• Main Purpose: Timing, Frequency Synthesizer
• Utilized Ic / Part: LMX2485E
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

1.7 DIGITAL LOCK DETECT OPERATION
The RF PLL digital lock detect circuitry compares the differ-
ence between the phase of the inputs of the phase detector
to a RC generated delay of ε. To indicate a locked state (Lock
= HIGH) the phase error must be less than the ε RC delay for
5 consecutive reference cycles. Once in lock (Lock = HIGH),
the RC delay is changed to approximately δ. To indicate an
out of lock state (Lock = LOW), the phase error must become
greater δ. The values of ε and δ are dependent on which PLL
is used and are shown in the table below:
When the PLL is in the power down mode and the Ftest/LD
pin is programmed for the lock detect function, it is forced
LOW. The accuracy of this circuit degrades at higher com-
parison frequencies. To compensate for this, the DIV4 word
should be set to one if the comparison frequency exceeds 20
MHz. The function of this word is to divide the comparison
frequency presented to the lock detect circuit by 4. Note that
if the MUX[3:0] word is set such as to view lock detect for both
PLLs, an unlocked (LOW) condition is shown whenever either
one of the PLLs is determined to be out of lock.
CE Pin
High
High
High
Low
PLL
RF
IF
RF_PD
X
X
0
1
Bit Enabled +
Write to RF
N Counter
ATPU
10 ns
15 ns
Yes
No
No
X
ε
( Asynchronous )
(Asynchronous)
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PLL State
20 ns
30 ns
δ
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