LMX2485E EVAL National Semiconductor, LMX2485E EVAL Datasheet - Page 24

• Manufacturer Part Number: LMX2485E EVAL
• Description: BOARD EVALUATION LMX2485E
• Manufacturer: National Semiconductor
• Series: PLLatinum™r

Specifications of LMX2485E EVAL

• Main Purpose: Timing, Frequency Synthesizer
• Utilized Ic / Part: LMX2485E
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -

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Quick Start Register Map
Although it is highly recommended that the user eventually take advantage of all the modes of the LMX2485, the quick start register
map is shown in order for the user to get the part up and running quickly using only those bits critical for basic functionality. The following
default conditions for this programming state are a third order delta-sigma modulator in 12-bit mode with no dithering and no Fastlock.
GIS
RE
TE
R0
R1 RF
R2 IF_
R3
R4
R
Programming Description
2.0 GENERAL PROGRAMMING INFORMATION
The 24-bit data registers are loaded through a MICROWIRE Interface. These data registers are used to program the R counter,
the N counter, and the internal mode control latches. The data format of a typical 24-bit data register is shown below. The control
bits CTL [3:0] decode the register address. On the rising edge of LE, data stored in the shift register is loaded into one of the
appropriate latches (selected by address bits). Data is shifted in MSB first. Note that it is best to program the N counter last, since
doing so initializes the digital lock detector and Fastlock circuitry. Note that initialize means it resets the counters, but it does NOT
program values into these registers. The exception is when 22-bit is not being used. In this case, it is not necessary to program
the R7 register.
2.0.1 Register Location Truth Table
The control bits CTL [3:0] decode the internal register address. The table below shows how the control bits are mapped to the
target control register.
2.0.2 Control Register Content Map
Because the LMX2485 registers are complicated, they are
organized into two groups, basic and advanced. The first four
registers are basic registers that contain critical information
PD
_P
23
D
0
RF
_P
22
0
0001
C3
x
0
0
0
1
1
1
1
21
1
20
0
RF_R[5:0]
DATA[19:0] ( Except for the RF_N Register, which is [22:0] )
19
RF_N[10:0]
0
RF_CPG[3:0]
18
0
17
0
C2
MSB
23
0
1
1
0
0
1
1
x
16
0
15
1
DATA [21:0]
14
1
IF_N[18:0]
13
0
12
0
C1
24
x
1
0
1
0
1
0
1
11
0
4 3
RF_FD[11:0]
necessary for the PLL to achieve lock. The last 5 registers are
for features that optimize spur, phase noise, and lock time
performance. The next page shows these registers.
IF_R[11:0]
10
1
CTL [3:0]
9
1
8
1
2 1
RF_FN[11:0]
LSB
7
0
C0
0
1
1
1
1
1
1
1
0
6
0
5
0
4
0
C3 C2
DATA Location
3
0
0
0
1
2
0
1
1
0
R0
R1
R2
R3
R4
R5
R6
R7
C1
1
1
0
1
0
C0
0
0
1
1
1
1