CDB4265 Cirrus Logic Inc, CDB4265 Datasheet - Page 10

BOARD EVAL FOR CS4265 CODEC

CDB4265

Manufacturer Part Number
CDB4265
Description
BOARD EVAL FOR CS4265 CODEC
Manufacturer
Cirrus Logic Inc
Datasheets

Specifications of CDB4265

Main Purpose
Audio, CODEC
Embedded
No
Utilized Ic / Part
CS4265
Primary Attributes
Stereo, 24-Bit, 192 kHz Sample Rate
Secondary Attributes
Graphic User Interface, S/PDIF/ I2S / I2C / SPI Interface
Description/function
Audio CODECs
Operating Supply Voltage
5 V
Product
Audio Modules
For Use With/related Products
CS4265
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
Other names
598-1001
CDB4265
3.4.2
SPDIF Recovered Clock - SPDIF In to DAC - ADC to SPDIF Out
Using the pre-configured script file named “SPDIF Recovered Clock - SPDIF In to DAC - ADC to SPDIF
Out.txt”, an analog input signal applied to the line level inputs of the CS4265 input multiplexer will be digi-
tized by the ADC and transmitted in S/PDIF format by the CS4265 internal S/PDIF transmitter. The S/PDIF
signal received by the CS8416 will be recovered, decoded into PCM, and routed to the CS4265 DAC where
it will be converted to analog by the DAC and output through the passive output filter. For proper operation
of this script, a valid S/PDIF signal must be applied.
The CS8416 recovered clock is the source of MCLK. The CS8416 is also the sub-clock master to the
CS4265 and the PCM I/O header.
10
DS657DB1

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