CDB4265 Cirrus Logic Inc, CDB4265 Datasheet
CDB4265
Specifications of CDB4265
Related parts for CDB4265
CDB4265 Summary of contents
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... Microphone Input Control Port Interface Cirrus Logic, Inc. www.cirrus.com Description The CDB4265 evaluation board is an excellent means for evaluating the CS4265 CODEC. Evaluation requires an analog/digital signal source and analyzer, and power supplies. A Windows used to evaluate the CS4265. System timing for the I²S, Left-Justified and Right-Justi- ...
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... Clock Routing ..................................................................................................................... 6 2.2 Data Routing ...................................................................................................................... 6 2.2.1 CS4265 SDIN1 and SDIN2 Source ....................................................................... 6 2.2.2 CS4265 TXSDIN Source ....................................................................................... SOFTWARE CONTROL ..................................................................................................... 7 3.1 CDB4265 Controls Tab ...................................................................................................... 7 3.2 S/PDIF Rx Controls Tab .................................................................................................... 8 3.3 Register Maps Tab ............................................................................................................. 9 3.4 Pre-Configured Script Files ................................................................................................ 9 3.4.1 Oscillator Clock - Line In to DAC & SPDIF Out ..................................................... 9 3 ...
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... LIST OF FIGURES Figure 1. CDB4265 Controls Tab.................................................................................................... 7 Figure 2. S/PDIF Rx Controls Tab .................................................................................................. 8 Figure 3. Register Maps Tab........................................................................................................... 9 Figure 4. Block Diagram................................................................................................................ 18 Figure 5. CS4265 .......................................................................................................................... 19 Figure 6. Analog Inputs ................................................................................................................. 20 Figure 7. Analog Outputs .............................................................................................................. 21 Figure 8. S/PDIF I/O...................................................................................................................... 22 Figure 9. Control Port.................................................................................................................... 23 Figure 10. FPGA ........................................................................................................................... 24 Figure 11. Discrete Clock Routing and Level Shifting................................................................... 25 Figure 12. Power........................................................................................................................... 26 Figure 13 ...
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... The FPGA handles both clock and data routing on the CDB4265. Clock and data routing selections made via the CDB4265 Controls tab in the GUI will be handled by the FPGA with no user intervention required. For advanced information regarding the internal registers and operation of the FPGA, see sections 4 and 5 beginning on page 11 ...
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... RCA jacks for easy evaluation. 1.10 Serial Control Port A graphical user interface is included with the CDB4265 to allow easy manipulation of the registers in the CS4265, CS8416, and FPGA. See the device-specific data sheets for the CS4265, CS8416, and CD8406 internal register descriptions. The internal register map for the FPGA is located in section 4 on page 11. ...
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... SYSTEM CLOCKS AND DATA The CDB4265 implements comprehensive clock and data routing capabilities. Configuration of the clock and data routing can be easily achieved using the controls within the Board Controls group box on the CDB4265 Controls tab in the GUI software application. 2.1 Clock Routing ...
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... The CDB4265 Controls tab provides a high-level intuitive interface to many of the configuration options of the CS4265 and CDB4265. The controls within the CS4265 Controls group box (with the exception of the AD0 control) control the internal registers of the CS4265. The controls within the Board Controls group box control the board level clock and data routing on the CDB4265 ...
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... S/PDIF Rx Controls Tab When the CDB4265 is configured to make use of the CS8416 S/PDIF receiver, these devices must be con- figured for proper operation. The S/PDIF Rx Controls tab provides a high-level intuitive interface to the most common configuration options of the CS8416. 8 Figure 2. S/PDIF Rx Controls Tab ...
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... Pre-Configured Script Files Pre-configured script files are provided with the CDB4265 to allow easy initial board bring-up. The board configurations stored within these files are described in sections 3.4.1 - 3.4.2. 3.4.1 Oscillator Clock - Line In to DAC & SPDIF Out Using the pre-configured script file named “ ...
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... DAC and output through the passive output filter. For proper operation of this script, a valid S/PDIF signal must be applied. The CS8416 recovered clock is the source of MCLK. The CS8416 is also the sub-clock master to the CS4265 and the PCM I/O header. 10 CDB4265 DS657DB1 ...
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... Source 0 04h Transmitter Reserved Reserved SDIN Source 0 DS657DB1 Rev6 Rev5 Rev4 MCLK1 MCLK0 Reserved Reserved Reserved Reserved SDIN2.2 SDIN2.1 SDIN2.0 Reserved Reserved Reserved Reserved CDB4265 Rev3 Rev2 Rev1 Reserved Reserved Reserved SUBCLK1 SDIN1.2 SDIN1 TXSDIN2 TXSDIN1 Rev0 x Reserved 0 SUBCLK0 1 SDIN1.0 0 TXSDIN0 1 ...
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... These bits select the source of the CS4265 MCLK signal. Table 1 shows the available settings. MCLK1 MCLK0 Rev4 Rev3 MCLK0 Reserved Table 1. MCLK Source MCLK Source Oscillator MCLK position on PCM Header (J15) CS8416 RMCK Reserved CDB4265 Rev2 Rev1 Rev0 Reserved Reserved Reserved DS657DB1 ...
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... Table 2. CS4265 Subclock Source CS4265 Subclock Source - CS4265 is Master - PCM Header Subclocks are Output from CS4265 Reserved - CS4265 is Slave to PCM Header - PCM Header Subclocks are an Input - CS4265 is Slave to CS8416 subclocks - PCM Header Subclocks are Output from CS8416 Subclocks CDB4265 Reserved SUBCLK1 SUBCLK0 13 ...
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... SDIN1 from Header 1 SDIN2 from Header 0 TXSDIN from Header 1 ... 1 Table 4. SDIN1 Source SDIN1 from Header 1 SDIN2 from Header 0 TXSDIN from Header 1 ... 1 CDB4265 2 1 SDIN1.2 SDIN1.1 SDIN2 Source CS8416 SDOUT CS4265 SDOUT Reserved SDIN1 Source CS8416 SDOUT CS4265 SDOUT Reserved DS657DB1 0 SDIN1.0 ...
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... These bits select the source of the CS4265 TXSDIN signal. Table 5 shows the available settings. TXSDIN2 TXSDIN1 TXSDIN0 ... ... 1 1 DS657DB1 Reserved Reserved Table 5. TXSDIN Source SDIN1 from Header 1 SDIN2 from Header 0 TXSDIN from Header 1 ... 1 CDB4265 2 1 TXSDIN2 TXSDIN1 TXSDIN Source CS8416 SDOUT CS4265 SDOUT Reserved 0 TXSDIN0 15 ...
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... CD-ROM type header for analog input signal to CS4265. Input 1/8“ TRS jacks for microphone input. Input RCA phono jacks for DAC analog outputs. Output Table 6. System Connections CDB4265 SIGNAL PRESENT 2 C control port signals 2 C control port signals control port signals. ...
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... Select RCA inputs as source. Line Input* Select TRS inputs as source. Mic Input Select RCA inputs as source. RCA* Select CD input as source. CD Local connection to board ground plane. GND* SGND signal from CD IN connector. SGND *Default factory settings Table 7. System Jumper Settings CDB4265 FUNCTION SELECTED 17 ...
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... CDB BLOCK DIAGRAM 18 CDB4265 DS657DB1 ...
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... CDB SCHEMATICS DS657DB1 CDB4265 19 ...
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... CDB4265 DS657DB1 ...
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... DS657DB1 CDB4265 21 ...
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... CDB4265 DS657DB1 ...
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... DS657DB1 CDB4265 23 ...
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... CDB4265 DS657DB1 ...
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... DS657DB1 CDB4265 25 ...
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... CDB4265 DS657DB1 ...
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... CDB LAYOUT DS657DB1 CDB4265 27 ...
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... CDB4265 DS657DB1 ...
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... DS657DB1 CDB4265 29 ...
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... Cirrus Logic, Cirrus, the Cirrus Logic logo designs, and Popguard are trademarks of Cirrus Logic, Inc. All other brand and product names in this doc- ument may be trademarks or service marks of their respective owners. Windows is a registered trademark of Microsoft Corporation. 30 Initial Release Table 8. Revision History CDB4265 Changes DS657DB1 ...