AD9911/PCBZ Analog Devices Inc, AD9911/PCBZ Datasheet - Page 29

• Manufacturer Part Number: AD9911/PCBZ
• Description: BOARD EVAL FOR AD9911
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9911/PCBZ

• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Utilized Ic / Part: AD9911
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant

I/O_UPDATE, SYNC_CLK, AND SYSTEM CLOCK
RELATIONSHIPS
I/O_UPDATE and SYNC_CLK are used together to transfer
data from the I/O buffer to the active registers in the device.
Data in the I/O buffer is inactive.
SYNC_CLK is a rising edge active signal. It is derived from
the system clock and a divide-by frequency divider of 4. The
SYNC_CLK is provided externally to synchronize external
hardware to the AD9911 internal clocks.
I/O_UPDATE initiates the start of a buffer transfer. It can be
sent synchronously or asynchronously relative to the
SYNC_CLK.
I/O BUFFERS
I/O UPDATE
REGISTERS
SYNC_CLK
DATA IN
SYSCLK
DATA IN
THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B.
N
N – 1
A
B
Figure 47. I/O_UPDATE Timing
N + 1
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If the set-up time between these signals is met, then constant
latency (pipeline) to the DAC output exists. For example, if
repetitive changes to phase offset via the SPI port is desired, the
latency of those changes to the DAC output is constant,
otherwise a time uncertainty of one SYNC_CLK period will be
present.
The I/O UPDATE is sampled on the rising edge of the
SYNC_CLK. Therefore, I/O_UPDATE must have a minimum
pulse width greater than one SYNC_CLK period.
The timing diagram shown in Figure 47 depicts when data in
the I/O buffer is transferred to the active registers.
The I/O UPDATE is set up and held around the rising edge of
SYNC_CLK and has zero hold time and 4.8 ns setup time.
N
N + 2
N
+ 1
AD9911