AD9911/PCBZ Analog Devices Inc, AD9911/PCBZ Datasheet - Page 19

• Manufacturer Part Number: AD9911/PCBZ
• Description: BOARD EVAL FOR AD9911
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9911/PCBZ

• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Utilized Ic / Part: AD9911
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant

MODES OF OPERATION
SINGLE-TONE MODE
To configure the AD9911 in single-tone mode, the auxiliary
DDS cores (CH0, CH2, and CH3) must be disabled by using the
channel enable bits and digital powering down (CSR bit <7>)
the three auxiliary DDS cores. Only CH1 remains enabled. See
the Register Maps section for a description of the channel
enable bits in the channel select register or CSR (Register 0x00).
The channel enable bits are enabled or disabled immediately
after the CSR data byte is written. An I/O_UPDATE is not
required for channel enable bits.
The two main registers used in this mode, Register 0x04 and
Register 0x05, contain the frequency tuning word and the phase
offset word for CH1. The following is a basic protocol to program a
frequency tuning word and/or phase offset word for CH1.
1.
2.
3.
4.
Single-Tone Mode—Matched Pipeline Delay
In single-tone mode, the AD9911 offers matched pipeline delay
to the DAC input for all frequency, phase, and amplitude
changes. The result is that frequency, phase, and amplitude
changes arrive at the DAC input simultaneously. The feature is
enabled by asserting the match pipeline delay bit found in the
channel function register (CSR) (Register 0x03). This feature is
available in single-tone mode only.
SPURKILLER/MULTITONE MODE
For both SpurKiller and multitone mode, the frequency, phase
and amplitude settings of the auxiliary channels and the
primary channel use Register 0x04 Bits <31:0> for frequency
and Register 0x05 Bits <13:0> for phase. Note the channel
enable bits in the CSR register must be use to distinguish the
content of each channel. See the I/O Port section for details.
Power up the AD9911 and issue a master reset. A master
reset places the part in single-bit mode for serial
programming operations (refer to the I/O Modes of
Operation section). The frequency tuning word and phase
offset word for CH1 defaults to 0.
Disable CH0, CH2, CH3 and enable CH1 using the
channel enable bits in Register 0x00.
Using the I/O port, program the desired frequency tuning
word (Register 0x04) and/or the phase offset word
(Register 0x05) for CH1.
Send an I/O update signal. CH1 should output its
programmed frequency and/or phase offset value, after a
pipeline delay (see Table 1).
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For multitone mode, the digital content of the three auxiliary
DDS channels are summed with the primary channel. Each
tone can be individually programmed for frequency, phase and
amplitude as well as individually modulated using the profile
pins in shift-keying modulation. See Figure 24 and Figure 27 for
examples.
Note the data align bits in Register 0x03 Bits <18:16>, provide a
coarse amplitude adjust setting for the auxiliary channels. These
bits default to clear; for multitone mode these bit should
typically be set.
For SpurKiller mode, the digital contents of the three auxiliary
DDS channels are attenuated and summed with the primary
channel. In this manner, harmonic spurs from the DAC can be
reduced. This is accomplished by matching the frequency of the
harmonic component, the amplitude, and the phase (180°
offset) of the desired spur on one of the SpurKiller channels.
Bench level observations and manipulation are required to
establish the optimal parameter settings for the SpurKiller
channel(s). The parameters are dependent on the fundamental
frequency and system clock frequency. The repeatability of
these settings on a unit-to-unit basis depends directly on the
SFDR variation of the DAC. The DAC on the AD9911 has
enough part-to-part SFDR variation that using a set of fixed
programming values across multiple devices will not
consistently improve SFDR.
Spur reduction performance on an individual device is stable
over supply and temperature. The SpurKiller/multitone mode
configuration is illustrated in Figure 36.
The amplitude of the auxiliary channels uses coarse and fine
adjustments to match the amplitude of the targeted spur. The
coarse adjust is implemented via the data align bits in Register
0x03 Bits <18:16>. The approximate amplitude of the auxiliary
channel is programmable between −60 dB and −12 dB com-
pared to the full-scale fundamental, per the following equation:
where AMP is the amplitude and D is the decimal value (0-7) of
the data align bits
For fine amplitude adjustments, the 10-bit output scalar
(multiplier) of the auxiliary channel in Register 0x06 Bit <0:9>
is used. The multiplier is enabled by Register 0x06 Bit <12>.
A single active SpurKiller channel targeting the second
harmonic is expressed as
where B × cos(2 ω t + Φ
tone of the SpurKiller channel.
AMP = −60 dB + (D × 6 dB)
f
× cos(2 ω t + Φ
OUT
= A × cos( ω t + Φ
2
+ 180°) + (all other spurious components)
2
+ 180°) represents the fundamental
1
) + B × cos(2 ω t + Φ
2
) + B
AD9911