AD9911/PCBZ Analog Devices Inc, AD9911/PCBZ Datasheet - Page 18

• Manufacturer Part Number: AD9911/PCBZ
• Description: BOARD EVAL FOR AD9911
• Manufacturer: Analog Devices Inc
• Series: AgileRF™r

Specifications of AD9911/PCBZ

• Main Purpose: Timing, Direct Digital Synthesis (DDS)
• Utilized Ic / Part: AD9911
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / RoHS Status: Supplier Unconfirmed, Lead free / RoHS Compliant

AD9911
THEORY OF OPERATION
PRIMARY DDS CORE
The AD9911 has one complete DDS (Channel 1) that consists
of a 32-bit phase accumulator, a phase-to-amplitude converter,
and 10-bit DAC. Together, these digital blocks generate a sine
wave when the phase accumulator is clocked and the phase
increment value (frequency tuning word) is greater than 0. The
phase-to-amplitude converter translates phase information to
amplitude information by a cos (θ) operation.
The output frequency (f
rollover rate of the phase accumulator. The exact relationship is
shown in the following equation:
where:
f
FTW = the frequency tuning word.
2
The DDS core architecture also supports the capability to phase
offset the output signal. This is performed by the channel phase
offset word (CPOW). The CPOW is a 14-bit register that stores
a phase offset value. This value is added to the output of the
phase accumulator to offset the current phase of the output
signal. The exact value of phase offset is given by the following
equation:
SPURKILLER/MULTITONE MODE AND TEST-TONE
MODULATION
The AD9911 is equipped with three auxiliary DDS cores
(Channel 0, Channel 2, and Channel 3). Because these channels
do not have a DAC, there is no direct output. Instead, these
channels are designed to implement either spur reduction/
multiple tones or test-tone modulation on the output spectrum
for Channel 1.
When using multitone mode, the device can output up to four
distinct carriers concurrently. This is possible via the summing
node for all four DDS cores. The frequency, phase and
amplitude of each tone is adjustable. The maximum amplitude
of the auxiliary channels is −12 db below the primary channel’s
maximum amplitude to prevent overdriving the DAC input.
The primary channel’s amplitude can be adjusted down to
achieve equal amplitude for all carriers.
When using SpurKiller mode, up to three spurs in the output
spectrum for Channel 1 are reducible (one per auxiliary
channel). To match an exact frequency using the three channels,
the spur must be harmonically related to the fundamental
S
32
= the system clock rate.
represents the capacity of the phase accumulator’ .
Φ
f
O
=
=
⎛
⎜
⎝
(
CPOW
FTW
2
2
14
32
)(
f
⎞
⎟
⎠
S
)
×
with
360
O
) of the DDS is a function of the
°
0
≤
FTW
≤
2
31
Rev. 0 | Page 18 of 44
frequency or the tuning word for Channel 1. A nonharmonic
spur may be impossible to match frequency.
Spur reduction is not as effective at lower fundamental
frequencies where SFDR performance is already very good. The
benefits of SpurKiller channels are virtually nonexistent when
the output frequency is less than 20% of the sampling
frequency.
Test-tone modulation is similar to amplitude modulation
options of a signal generator. For test-tone modulation,
auxiliary DDS Channel 0 is assigned to implement amplitude
sinusoidal modulated waveforms of the primary channel. This
function is programmed using internal registers.
D/A CONVERTER
The AD9911 incorporates a 10-bit current output DAC. The
DAC converts a digital code (amplitude) into a discrete analog
quantity. The DAC current outputs can be modeled as a current
source with high output impedance (typically 100 kΩ). Unlike
many DACs, these current outputs require termination into
AVDD via a resistor or a center-tapped transformer for
expected current flow.
The DAC has complementary outputs that provide a combined
full-scale output current (I
current.
The full-scale current is controlled by means of an external
resistor (R
discussed in the Modes of Operation section. The Resistor R
is connected between the DAC_RSET pin and analog ground
(AGND). The full-scale current is inversely proportional to the
resistor value as follows:
Limiting the output to 10 mA with an R
optimal spurious-free dynamic range (SFDR) performance. The
DAC output voltage compliance range is AVDD + 0.5 V to
AVDD − 0.5 V. Voltages developed beyond this range can cause
excessive harmonic distortion. Proper attention should be paid
to the load termination to keep the output voltage within its
compliance range. Exceeding this range could damage the DAC
output circuitry.
I
OUT
Figure 35. Typical DAC Output Termination Configuration
SET
=
18
) and the scalable DAC current control bits
R
DAC
SET
.
91
I
I
OUT
OUT
AVDD
OUT
+ I
1:1
OUTB
). The outputs always sink
B
SET
LPF
of 1.9 kΩ provides
50Ω
SET