EVAL-ADF4118EB1 Analog Devices Inc, EVAL-ADF4118EB1 Datasheet - Page 18
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EVAL-ADF4118EB1
Manufacturer Part Number
EVAL-ADF4118EB1
Description
BOARD EVAL FOR ADF4118
Manufacturer
Analog Devices Inc
Datasheet
1.ADF4116BRUZ-REEL.pdf
(28 pages)
Specifications of EVAL-ADF4118EB1
Main Purpose
Timing, Frequency Synthesizer
Embedded
No
Utilized Ic / Part
ADF4118
Primary Attributes
Single Integer-N PLL
Secondary Attributes
1.96GHz WCDMA, Graphical User Interface
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
ADF4116/ADF4117/ADF4118
CE PIN PD2 PD1
0
1
1
1
DB20
X
X
X
0
1
DB19
PD2
X
0
1
1
ASYNCHRONOUS POWER-DOWN
NORMAL OPERATION
ASYNCHRONOUS POWER-DOWN
SYNCHRONOUS POWER-DOWN
DB18
X
RESERVED
DB17
X
MODE
TC4
DB16
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
DB15
TC4
TC3
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
TIMER COUNTER
DB14
TC3
CONTROL
TC2
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
DB13
TC2
Figure 34. Initialization Latch Map
DB12
TC1
F4
0
1
1
TC1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Rev. D | Page 18 of 28
DB11
F6
X
0
1
F6
(PFD CYCLES)
TIMEOUT
FASTLOCK DISABLED
FASTLOCK MODE 1
FASTLOCK MODE 2
FASTLOCK MODE
DB10
11
15
19
23
27
31
35
39
43
47
51
55
59
63
X
3
7
DB9
F4
F3
DB8
0
1
F3
NORMAL
THREE-STATE
CHARGE PUMP
F2
DB7
0
1
F2
OUTPUT
PHASE DETECTOR
DB6
M3
NEGATIVE
POLARITY
POSITIVE
M3
0
0
0
1
1
1
1
0
CONTROL
MUXOUT
DB5
M2
M2
0
0
1
1
0
0
1
1
DB4
M1
M1
0
1
0
1
0
1
0
1
DB3
PD1
THREE-STATE OUTPUT
DIGITAL LOCK DETECT
(ACTIVE HIGH)
N DIVIDER OUTPUT
AV
R DIVIDER OUTPUT
ANALOG LOCK DETECT
(N CHANNEL OPEN DRAIN)
SERIAL DATA OUTPUT
(INVERSE POLARITY OF
SERIAL DATA INPUT)
DGND
F1
0
1
DD
DB2
F1
NORMAL
R, A, B COUNTERS
HELD IN RESET
OPERATION
OUTPUT
COUNTER
C2 (1)
DB1
CONTROL
BITS
C1 (1)
DB0