DK-SI-4S100G2N Altera, DK-SI-4S100G2N Datasheet - Page 18

• Manufacturer Part Number: DK-SI-4S100G2N
• Description: KIT DEV STRATIX IV TRANSCEIVER
• Manufacturer: Altera
• Series: Stratix® IVr

Specifications of DK-SI-4S100G2N

• Main Purpose: *
• Embedded: *
• Utilized Ic / Part: EP4S100G2F40C2ES1
• Primary Attributes: *
• Secondary Attributes: *
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP4S
• Silicon Family Name: Stratix IV GT
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2603

6–4
Transceiver Signal Integrity Development Kit, Stratix IV GT Edition User Guide
1
Analog Settings
You can use the application to dynamically control transceiver PMA settings for the
different transceiver blocks. The following list defines the analog setting parameters
in the control panel window:
Resets
The following list describes the available resets:
After the System Reset is asserted, the DataChk Status may show unsynced for some
channels due to the asynchronous nature of the reset. Asserting the Data Patrst
synchronizes the error checker to the transmitted data.
Help
The Help button displays the image of the Stratix IV signal integrity board and also
highlights the channel locations and their data rates based on the .sof loaded.
Power Down
Turn on Powerdown to power down the transceiver block.
Serial Loopback
Serial loopback is available for all the channels and can be controlled during run time.
After the serial loopback status in the interface changes, the DataChk Status field
may show unsynced for some channels due to the asynchronous nature of the serial
loopback signal. The Data Patrst should be asserted in this case to synchronize the
error checker with the transmitted data.
Data Patterns
The application supports high- and low-frequency patterns for PRBS15i, PRBS7,
PRBS23 and PRBS31. No synchronization patterns are sent prior to sending the PRBS
pattern. Therefore, you can use a third party receiver to recognize the PRBS data.
Data verifiers are not available for the high frequency (1010..) and low frequency (5’1s
and 5’0s) patterns.
Parameter
VOD
EQ
Gain
PE
Reset
System
Error
Description
Reset for the transceiver.
Reset for all the error counters to zero.
Description
differential output driver voltage.
equalization.
DC gain.
preemphasis/deemphasis.
pre, 1stpost, and 2ndpost settings represent different taps.
Chapter 6: Stratix IV GT Transceiver Signal Integrity Demonstration
Running the Demonstration Application and Test Designs
© December 2009 Altera Corporation