HW-FMC-VIDEO-DC-G Xilinx Inc, HW-FMC-VIDEO-DC-G Datasheet - Page 22

• Manufacturer Part Number: HW-FMC-VIDEO-DC-G
• Description: HARDWARE FMC-VIDEO DAUGHTER CARD
• Manufacturer: Xilinx Inc

Specifications of HW-FMC-VIDEO-DC-G

• Accessory Type: Daughter Card
• For Use With/related Products: Spartan 3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 2: Hardware Overview
Signal Bus Multiplexing
FMC Low Pin Count Connector
22
DVI Bus Multiplexing
Video Input Multiplexing
Standard Pinout
Analog and digital power supplies are isolated using ferrites and proper grounding
layout.
Because of the large number of signals required by each of the video interfaces and the
limited number of signals on the FMC connector, it is not possible to dedicate a connector
pin for each of the data bits. To fit within the connector signal count, some signals must be
shared. Rather than using traditional bus multiplexor ICs, which add cost, board space,
and latency to the signals, some of the signals can be multiplexed by sharing nets and
controlling the signal output enables. This was done with two pairs of data buses.
The DVIIN_x signals are shared between the DVI analog interface and the DVI digital
receiver. The DVI receiver outputs are high-impedance when the PDO_L pin is asserted
Low. This pin is controlled by the DVIIN_OE signal on the I
of this is Low, not enabled. The outputs of the DVI analog interface, the AD9884A, can be
disabled through its I
contention, only one of these interfaces can be enabled at a time.
Note:
receiver is only 8 bits. This means that two of the bits are not shared. These signals were connected
such that the two devices use the same bit as the most significant bit, bit 9. The digital receiver does
not use bits 1 and 0.
The VIDIN_x signals are shared between the video decoder and camera 1. The camera 1
signals are set to high impedance using the REN pin on the deserializer, driven by the net
CAM1_OE, from the I
of the video decoder, the ADV7180, are disabled through its I
default state is enabled. To prevent bus contention only one of these interfaces can be
enabled at a time.
The VITA-57 FMC connector is of the low-pin-count (LPC) variant. All I/O on this
connector shall be 3.3V single ended, with the exception of two LVDS clocks. The available
pins in the LPC connector are in rows C, D, G, and H, as shown in
The data width from the analog interface is 10 bits, while the data width from the digital
2
2
C control registers. Its default state is output enabled. To prevent bus
C I/O expander. The default state is Low, not enabled. The outputs
www.xilinx.com
2
C I/O expander. The default
2
UG458 (v1.1) February 8, 2008
C control registers. The
FMC-Video Daughter Board
Figure
2-6.
R