MT9HTF6472AY-667D4 Micron Technology Inc, MT9HTF6472AY-667D4 Datasheet - Page 28

• Manufacturer Part Number: MT9HTF6472AY-667D4
• Description: MODULE DDR2 512MB 240-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9HTF6472AY-667D4

• Memory Type: DDR2 SDRAM
• Memory Size: 512MB
• Package / Case: 240-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Speed: -
• Other names: 557-1303; MT9HTF6472AY-667D4

Table 15:
pdf: 09005aef80e6f860, source: 09005aef80e5b799
HTF9C32_64_128x72AG_2.fm - Rev. C 6/05 EN
Parameter/Condition
Operating one device bank active-precharge current;
=
commands; Address bus inputs are SWITCHING; Data bus inputs are
SWITCHING.
Operating one device bank active-read-precharge current; I
BL = 4, CL = CL(I
(I
Address bus inputs are SWITCHING; Data pattern is same as I
Precharge power-down current; All device banks idle;
LOW; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING.
Precharge quiet standby current; All device banks idle;
is HIGH, S# is HIGH; Other control and address bus inputs are STABLE; Data bus
inputs are FLOATING.
Precharge standby current; All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are SWITCHING; Data
bus inputs are SWITCHING.
Active power-down current; All device banks open;
t
STABLE; Data bus inputs are FLOATING.
Active standby current;
All device banks open;
CKE is HIGH, S# is HIGH between valid commands; Other control and address
bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Operating burst write current; All device banks open, Continuous burst
writes; BL = 4, CL = CL (I
t
are SWITCHING; Data bus inputs are SWITCHING.
Operating burst read current; All device banks open, Continuous burst
reads, I
(I
bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Burst refresh current;
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING.
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and address
bus inputs are FLOATING; Data bus inputs are FLOATING.
Operating device bank interleave read current; All device banks
interleaving reads, I
(I
HIGH, S# is HIGH between valid commands; Address bus inputs are STABLE
during DESELECTs; Data bus inputs are SWITCHING; See I
detail.
CK (I
RP (I
DD
DD
DD
t
RC (I
),
),
);
DD
DD
t
t
t
RP =
RCD =
CK =
DD
OUT
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs
); CKE is LOW; Other control and address bus inputs are
),
= 0mA; BL = 4, CL = CL (I
t
t
t
RP (I
RAS =
CK (I
t
DDR2 I
Values shown for DDR2 SDRAM components only
RCD (I
DD
DD
DD
), AL = 0;
t
); CKE is HIGH, S# is HIGH between valid commands; Address
RAS MIN (I
),
DD
OUT
t
DD
RC =
); CKE is HIGH, S# is HIGH between valid commands;
t
DD
= 0mA; BL = 4, CL = CL (I
CK =
t
CK =
Specifications and Conditions – 256MB
), AL = 0;
t
t
RC(I
CK =
t
CK(I
DD
t
CK (I
DD
256MB, 512MB, 1GB (x72, SR, ECC) 240-Pin DDR2 SDRAM UDIMM
); CKE is HIGH, S# is HIGH between valid
t
DD
),
CK (I
DD
t
CK =
DD
t
),
RRD =
), AL = 0;
t
); Refresh command at every
RAS =
DD
t
CK (I
),
t
t
RC =
RRD(I
t
RAS MAX (I
DD
t
CK =
DD
),
t
DD
RC (I
), AL =
t
RAS =
t
),
t
CK (I
CK =
t
DD
RCD =
t
CK =
DD
),
t
t
t
DD
DD
CK =
RCD (I
RAS MAX (I
t
t
t
CK (I
7 Conditions for
t
RAS =
CK =
),
28
),
CK =
DD
t
t
t
RCD(I
RAS =
RP =
4W.
t
DD
CK (I
DD
t
Fast PDN Exit
MR[12] = 0
Slow PDN Exit
MR[12] = 1
t
CK (I
OUT
CK (I
t
); CKE is
)-1 x
RAS MIN
t
t
DD
RFC (I
RP(I
DD
t
RAS MAX
DD
= 0mA;
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
); CKE is
DD
); CKE is
t
),
DD
CK
); CKE
),
t
DD
RP =
);
t
I
RC
)
DD
Specifications and Conditions
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
I
I
DD
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
2P
3P
4R
0
1
5
6
7
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
1,710
1,620
1,620
2,250
-667
810
900
360
360
270
450
45
54
45
1,440
1,350
1,530
2,160
-53E
720
810
315
315
225
360
45
54
45
1,125
1,035
1,485
2,070
-40E
675
765
225
270
180
270
45
54
45
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA