MT9HTF6472FY-53EB4E3 Micron Technology Inc, MT9HTF6472FY-53EB4E3 Datasheet - Page 11

• Manufacturer Part Number: MT9HTF6472FY-53EB4E3
• Description: MODULE DDR2 512MB 240FBDIMM
• Manufacturer: Micron Technology Inc

Specifications of MT9HTF6472FY-53EB4E3

• Memory Type: DDR2 SDRAM
• Memory Size: 512MB
• Speed: 533MT/s
• Package / Case: 240-FBDIMM
• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240FBDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 512Mb
• Package Type: FBDIMM
• Maximum Clock Rate: 533MHz
• Operating Supply Voltage (typ): 1.8V
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Serial Presence-Detect
Table 17:
Table 18:
PDF: 09005aef81a2f1eb/Source: 09005aef81a2f20c
HTF9C64_128x72F.fm - Rev. B 9/07 EN
Parameter/Condition
Parameter/Condition
EEPROM and AMB supply voltage
Input high voltage: logic 1; all inputs
Input low voltage: logic 0; all inputs
Output low voltage: I
Input leakage current: V
Output leakage current: V
Standby current
Power supply current, READ: SCL clock frequency = 100 kHz
Power supply current, WRITE: SCL clock frequency = 100 kHz
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Serial Presence-Detect EEPROM DC Operating Conditions
Serial Presence-Detect EEPROM AC Operating Conditions
Notes:
OUT
IN
= 3mA
OUT
= GND to V
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1 and
2. This parameter is sampled.
3. For a restart condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
= GND to V
the falling or rising edge of SDA.
sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tance, and the EEPROM does not respond to its slave address.
DD
DD
512MB, 1GB (x72, SR) 240-Pin DDR2 SDRAM FBDIMM
11
t
WRC) is the time from a valid stop condition of a write
t
Symbol
t
t
t
t
HD:DAT
HD:STA
SU:DAT
SU:STO
SU:STA
t
Symbol
t
t
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
HIGH
V
LOW
f
WRC
t
t
BUF
SCL
AA
DH
t
t
DDSPD
I
t
V
I
R
V
F
I
CC
I
V
I
CC
I
LO
SB
OL
LI
IH
IL
W
R
V
Min
200
100
0.2
1.3
0.6
0.6
0.6
1.3
0.6
DDSPD
–
0
–
–
–
–
Min
–0.6
0.10
0.05
3.0
1.6
0.4
2.0
–
× 0.7
Serial Presence-Detect
Max
©2005 Micron Technology, Inc. All rights reserved.
300
400
0.9
0.3
50
10
–
–
–
–
–
–
–
–
–
V
V
DDSPD
DDSPD
Max
3.6
0.4
3.0
3.0
4.0
1.0
3.0
Units
kHz
+ 0.5
× 0.3
ms
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
Notes
Units
mA
mA
µA
µA
µA
V
V
V
V
1
2
2
3
4