MT4VDDT864AG-265B1 Micron Technology Inc, MT4VDDT864AG-265B1 Datasheet - Page 21

• Manufacturer Part Number: MT4VDDT864AG-265B1
• Description: MODULE SDRAM DDR 64MB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT864AG-265B1

• Memory Type: DDR SDRAM
• Memory Size: 64MB
• Speed: 266MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

pdf: 09005aef8085081a, source: 09005aef806e129d
DD4C8_16_32x64AG.fm - Rev. B 9/04 EN
35. V
36. V
37.
38.
39. During initialization, V
40. For -335, -262, -26A and -265 speed grades, I
80
70
60
50
40
30
20
10
g. The voltage levels used are derived from a mini-
Figure 9: Reduced Drive Pull-Down
0
0.0
f )The full variation in the ratio of the nominal
pulse width ≤ 3ns and the pulse width can not be
greater than 1/3 of the cycle rate. VIL undershoot:
V
pulse width can not be greater than 1/3 of the
cycle rate.
t
+
over
t
referenced to a specific voltage level but specify
when the device output is no longer driving
(
be equal to or less than V
V
even if V
42Ω of series resistance is used between the V
supply and the input pin.
is specified to be 35mA per DDR SDRAM at 100
MHz.
HZ (MAX) takes precedence over
RPST end point and
t
IH
IL
DD
RPST), or begins driving (
TT
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source voltages
from 0.1V to 1.0V.
mum V
practice, the voltage levels obtained from a
properly terminated bus will provide signifi-
cantly different voltage values.
t
RPST (MAX) condition.
(MIN) = -1.5V for a pulse width ≤ 3ns and the
overshoot: V
and V
may be 1.35V maximum during power up,
t
DQSCK (MIN) +
DD
DD
0.5
DD
/V
Characteristics
level and the referenced test load. In
Q must track each other.
DD
Q are 0V, provided a minimum of
IH
1.0
(MAX) = V
t
RPRE (MAX) condition.
t
V
RPRE begin point are not
OUT
DD
(V)
DD
Q, V
t
t
RPRE).
LZ (MIN) will prevail
1.5
+ 0.3V. Alternatively,
TT
DD
, and V
t
Q + 1.5V for a
DQSCK (MAX)
2.0
Minimum
REF
DD
must
3N
TT
2.5
21
41. The current Micron part operates below the slow-
42. Random addressing changing and 50 percent of
43. Random addressing changing and 100 percent of
44. CKE must be active (high) during the entire time a
45. I
46. Whenever the operating frequency is altered, not
47. Leakage number reflects the worst case leakage
48. When an input signal is HIGH or LOW, it is
49. The -335 speed grade will operate with
64MB, 128MB, 256MB (x64, SR)
-10
-20
-30
-40
-50
-60
-70
-80
0
0.0
Figure 10: Reduced Drive Pull-Up
est JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
data changing at every transfer.
data changing at every transfer.
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
t
to a valid high or low logic level. I
to I
control inputs to remain stable. Although IDD2F,
I
case.”
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
possible through the module pin, not what each
memory device contributes.
defined as a steady state logic HIGH or LOW.
= 40ns and
frequency.
REF later.
DD
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
184-PIN DDR SDRAM UDIMM
2
2
DD
N
N
, and I
2
specifies the DQ, DQS, and DM to be driven
F
0.5
except I
t
RAS (MAX) = 120,000ns at any slower
Characteristics
DD
2
DD
Q
1.0
V
2
are similar, I
DD
Q
Q - V
specifies the address and
OUT
(V)
1.5
©2004 Micron Technology, Inc.
DD
DD
2
2
2.0
F
Q
t
RAS (MIN)
Nominal low
Minimum
is “worst
is similar
2.5