MT4VDDT864AG-265B1 Micron Technology Inc, MT4VDDT864AG-265B1 Datasheet - Page 19

• Manufacturer Part Number: MT4VDDT864AG-265B1
• Description: MODULE SDRAM DDR 64MB 184DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT864AG-265B1

• Memory Type: DDR SDRAM
• Memory Size: 64MB
• Speed: 266MT/s
• Package / Case: 184-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

pdf: 09005aef8085081a, source: 09005aef806e129d
DD4C8_16_32x64AG.fm - Rev. B 9/04 EN
22. The valid data window is derived by achieving
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not
25. To maintain a valid level, the transitioning edge of
140.6µs (64MB) or 70.3µs (128MB, 256MB); burst
refreshing or posting by the DRAM controller
greater than eight refresh cycles is not allowed.
other specifications:
(
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/55, beyond which functionality is
uncertain. Figure 6, Derating Data Valid Window
(t
cycles ranging between 50/50 and 45/55.
result in a fail value. CKE is HIGH during
REFRESH command period (
CKE is LOW (i.e., during standby).
the input must:
a. Sustain a constant slew rate from the current
b. Reach at least the target AC level.
t
QH =
QH =
AC level through to the target AC level, V
or V
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
t
t
IH
HP -
HP -
(AC).
50/50
3.750
2.500
t
t
QHS), shows derating curves for duty
QHS). The data valid window derates
NA
49.5/50.5
3.700
-335
-262/-26A/-265 @
-262/-26A/-265 @
t
2.463
HP (
t
Figure 6: Derating Data Valid Window
CK/2),
3.650
49/51
2.425
t
t
t
RFC [MIN]) else
CK = 10ns
CK = 7.5ns
t
DQSQ, and
48.5/52.5
3.600
2.388
(t
IL
QH =
(AC)
t
48/52
3.550
QH
2.350
Clock Duty Cycle
t
HP -
19
47.5/53.5
3.500
26. JEDEC specifies CK and CK# input slew rate must
27. DQ and DM input slew rates must not deviate
28. V
29. The clock is allowed up to ±150ps of jitter. Each
30.
31. READs and WRITEs with auto precharge are not
t
2.313
QHS)
64MB, 128MB, 256MB (x64, SR)
be ≥ 1V/ns (2V/ns differentially).
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to
t
slew rate exceeds 4V/ns, functionality is uncer-
tain.
not active while any bank is active.
timing parameter is allowed to vary by the same
amount.
t
minimum actually applied to the device CK and
CK# inputs, collectively during bank active.
allowed to be issued until
fied prior to the internal precharge command
being issued.
c. After the AC target level is reached, continue to
DH for each 100mv/ns reduction in slew rate. If
HP min is the lesser of
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
184-PIN DDR SDRAM UDIMM
maintain at least the target DC level, V
or V
47/53
3.450
must not vary more than 4 percent if CKE is
2.275
IH
(DC).
46.5/54.5
3.400
2.238
3.350
46/54
2.200
t
t
RAS (MIN) can be satis-
CL minimum and
45.5/55.5
3.300
2.163
©2004 Micron Technology, Inc.
3.250
45/55
2.125
t
DS and
IL
(DC)
t
CH