MT18VDDF12872HY-335D1 Micron Technology Inc, MT18VDDF12872HY-335D1 Datasheet - Page 18
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MT18VDDF12872HY-335D1
Manufacturer Part Number
MT18VDDF12872HY-335D1
Description
MODULE SDRAM DDR 512MB 200SODIMM
Manufacturer
Micron Technology Inc
Datasheet
1.MT18VDDF12872HY-335D1.pdf
(27 pages)
Specifications of MT18VDDF12872HY-335D1
Memory Type
DDR SDRAM
Memory Size
1GB
Speed
333MT/s
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
200SODIMM
Device Core Size
72b
Organization
128Mx72
Total Density
1GByte
Chip Density
512Mb
Access Time (max)
700ps
Maximum Clock Rate
333MHz
Operating Supply Voltage (typ)
2.5V
Operating Current
1.53A
Number Of Elements
18
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
0C to 65C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
09005aef80e487d7
DDF18C64_128x72HG_A.fm - Rev. A 10/03 EN
21. The refresh period 64ms. This equates to an aver-
22. The valid data window is derived by achieving
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not
age refresh rate of 7.8125µs. However, an AUTO
REFRESH command must be asserted at least
once every 70.3µs; burst refreshing or posting by
the DRAM controller greater than eight refresh
cycles is not allowed.
other specifications:
(
directly porportional with the clock duty cycle
and a practical data valid window can be derived.
The clock is allowed a maximum duty cycle varia-
tion of 45/55, beyon which functionality is uncer-
tain. Figure 7, Derating Data Valid Window, shows
derating curves for duty cycles ranging between
50/50 and 45/55.
result in a fail value. CKE is HIGH during
REFRESH command period (
CKE is LOW (i.e., during standby).
t
QH =
3.8
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
1.8
t
HP -
50/50
3.750
2.500
t
QHS). The data valid window derates
NA
49.5/50.5
3.700
-335
-262/-26A/-265 @ t CK = 10ns
-262/-26A/-265 @ t CK = 7.5ns
2.463
t
HP (
t
Figure 7: Derating Data Valid Window
CK/2),
3.650
49/51
2.425
t
RFC [MIN]) else
t
DQSQ, and
48.5/52.5
3.600
2.388
3.550
48/52
t
QH
2.350
Clock Duty Cycle
18
47.5/53.5
3.500
25. To maintain a valid level, the transitioning edge of
26. JEDEC specifies CK and CK# input slew rate must
27. DQ and DM input slew rates must not deviate
28. V
29. The clock is allowed up to ±150ps of jitter. Each
2.313
the input must:
be ³ 1V/ns (2V/ns differentially).
from DQS by more than 10 percent. If the DQ/
DM/DQS slew rate is less than 0.5V/ns, timing
must be derated: 50ps must be added to
t
slew rate exceeds 4V/ns, functionality is uncer-
tain. For -335, slew rates must be ³ 0.5 V/ns.
not active while any bank is active.
timing parameter is allowed to vary by the same
amount.
a. Sustain a constant slew rate from the current
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to
DH for each 100mv/ns reduction in slew rate. If
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
AC level through to the target AC level, V
or V
maintain at least the target DC level, V
or V
3.450
47/53
512MB, 1GB (x72, ECC, DR)
must not vary more than 4 percent if CKE is
2.275
IH
IH
(AC).
(DC).
46.5/54.5
200-PIN DDR SODIMM
3.400
2.238
3.350
46/54
2.200
45.5/55.5
3.300
2.163
©2003 Micron Technology, Inc.
3.250
45/55
t
DS and
2.125
IL
IL
(DC)
(AC)