MT18LSDT6472G-13ED2 Micron Technology Inc, MT18LSDT6472G-13ED2 Datasheet - Page 9

• Manufacturer Part Number: MT18LSDT6472G-13ED2
• Description: MODULE SDRAM 512MB 168DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18LSDT6472G-13ED2

• Memory Type: SDRAM
• Memory Size: 512MB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 4831838208
• Chip Density: 256Mb
• Access Time (max): 5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 2.43A
• Number Of Elements: 18
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

and the latency is m clocks, the data will be available
by clock edge n + m. The DQs will start driving as a
result of the clock edge one cycle earlier (n + m - 1),
and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example,
assuming that the clock cycle time is such that all rele-
vant access times are met, if a read command is regis-
tered at T0 and the latency is programmed to two
clocks, the DQs will start driving after T1 and the data
will be valid by T2, as shown in the CAS Latency Dia-
gram. The CAS Latency Table indicate the operating
frequencies at which each CAS latency setting can be
used.
operation or incompatibility with future versions may
result.
Operating Mode
M7 and M8 to zero; the other combinations of values
for M7 and M8 are reserved for future use and/or test
modes. The programmed burst length applies to both
read and write bursts.
because unknown operation or incompatibility with
future versions may result.
Write Burst Mode
M9 = 1, the programmed burst length applies to
(nonburst) accesses.
16,32,Meg x 64 DDR SDRAM DIMMs (Footer Desc variable)
SD18C16_32_64x72G_B.fm - Rev. B 1/03 EN
If a READ command is registered at clock edge n,
Reserved states should not be used as unknown
The normal operating mode is selected by setting
Test modes and reserved states should not be used
When M9 = 0, the burst length programmed via
M0-M2 applies to both read and write bursts; when
read bursts, but write accesses are single-location
168-PIN REGISTERED SDRAM DIMM
9
128MB, 256MB, 512MB (x72, ECC)
Table 8:
Registered mode will add one clock cycle to CAS Latency
(CL) listed
COMMAND
COMMAND
SPEED
CLK
CLK
-13E
-133
-10E
DQ
DQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 5: CAS Latency Diagram
READ
READ
T0
T0
CAS Latency Table
CAS Latency = 2
CL = 2
£ 133
£ 100
£ 100
ALLOWABLE OPERATING
NOP
NOP
T1
T1
t
t AC
LZ
CAS Latency = 3
FREQUENCY (MHZ)
T2
NOP
T2
NOP
t
t AC
LZ
D
t OH
OUT
©2003, Micron Technology Inc.
CL = 3
£ 143
£ 133
NA
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
T4