MT16LSDT12864AG-13EC1 Micron Technology Inc, MT16LSDT12864AG-13EC1 Datasheet - Page 4

• Manufacturer Part Number: MT16LSDT12864AG-13EC1
• Description: MODULE SDRAM 1GB 168DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16LSDT12864AG-13EC1

• Memory Type: SDRAM
• Memory Size: 1GB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 5:
PDF: 09005aef8088b2e3/Source: 09005aef8088077a
SD8_16C64_128x64AG.fm - Rev. C 6/05 EN
97–101, 103–104, 139–142,
6, 18, 26, 40, 41, 49, 59, 73,
1, 12, 23, 32, 43, 54, 64, 68,
84, 90, 102, 110, 124, 133,
33–38, 117–121, 123, 126
78, 85, 96, 107, 116, 127,
2–5, 7–11, 13–17, 19–20,
55–58, 60, 65–67, 69–72,
28, 29, 46, 47, 112, 113,
74–77, 86–89, 91–95,
138, 148,. 152, 162
153–156,158–161
42, 79, 125, 163
30, 45,114, 129
Pin Numbers
144, 149–151,
143, 157, 168
27, 111, 115
130, 131
165–167
63, 128
39, 122
83
82
Pin Descriptions
Pin numbers may not correlate with symbols. Refer to Table 4 on page 3 for pin number and symbol
information.
RAS#, CAS#,
CKE0, CKE1
DQ0–DQ63
BA0, BA1
CK0–CK3
DQMB0–
SA0–SA2
Symbol
S0#–S3#
DQMB7
A0–A12
WE#
SDA
V
SCL
V
DD
SS
Output
Output
Supply
Supply
Input/
Input/
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM
Description
Command inputs: RAS#, CAS#, and WE# (along with S#) define the
command being entered.
Clock: CK is driven by the system clock. All SDRAM input signals are
sampled on the positive edge of CK. CK also increments the internal
burst counter and controls the output registers.
Clock enable: CKE activates (HIGH) and deactivates (LOW) the CK
signal. Deactivating the clock provides PRECHARGE POWER-DOWN
and SELF REFRESH operation (all device banks idle) or CLOCK
SUSPEND OPERATION (burst access in progress). CKE is synchronous
except after the device enters power- down and self refresh modes,
where CKE becomes asynchronous until after exiting the same
mode. The input buffers, including CK, are disabled during power-
down and self refresh modes, providing low standby power.
Chip select: S# enables (registered LOW) and disables (registered
HIGH) the command decoder. All commands are masked when S# is
registered HIGH. S# is considered part of the command code.
Input/Output mask: DQMB is an input mask signal for write accesses
and an output enable signal for read accesses. Input data is masked
when DQMB is sampled HIGH during a WRITE cycle. The output
buffers are placed in a High-Z state (two-clock latency) when DQMB
is sampled HIGH during a READ cycle.
Bank address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE, or PRECHARGE command is being applied.
Address inputs: Provide the row address for ACTIVE commands, and
the column address and auto precharge bit (A10) for READ/WRITE
commands, to select one location out of the memory array in the
respective device bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one
device bank (A10 LOW, device bank selected by BA0, BA1) or all
device banks (A10 HIGH). The address inputs also provide the op-
code during a MODE REGISTER SET command.
Serial clock for presence-detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
Presence-Detect address Inputs: These pins are used to configure the
presence-detect device.
Data I/O: Data bus.
Serial presence-detect data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-detect
portion of the module.
Power supply: +3.3V ±0.3V.
Ground.
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
©2002 Micron Technology, Inc. All rights reserved.