MT16LSDT12864AG-13EC1 Micron Technology Inc, MT16LSDT12864AG-13EC1 Datasheet - Page 13

• Manufacturer Part Number: MT16LSDT12864AG-13EC1
• Description: MODULE SDRAM 1GB 168DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16LSDT12864AG-13EC1

• Memory Type: SDRAM
• Memory Size: 1GB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Commands
Table 8:
PDF: 09005aef8088b2e3/Source: 09005aef8088077a
SD8_16C64_128x64AG.fm - Rev. C 6/05 EN
Name (Function)
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh
mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
Truth Table – SDRAM Commands and DQMB Operation
CKE is HIGH for all commands shown except SELF REFRESH; notes appear following the Truth Table
Notes: 1. A0–A12 provide row address; BA0–BA1 determine which device bank is made active.
Table 8 provides a quick reference of available commands. This is followed by a written
description of each command. For a more detailed description of commands and oper-
ations, refer to the 512Mb SDRAM component data sheet.
2. A0–A9, A11 provide column address; A10 HIGH enables the auto-precharge feature (non-
3. A10 LOW: BA0–BA1 determine which device bank is being precharged. A10 HIGH: all
4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care”
6. A0–A11 define the op-code written to the mode register and A12 should be driven LOW.
7. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock
persistent), while A10 LOW disables the auto-precharge feature; BA0–BA1 determine
which device bank is being read from or written to.
device banks are precharged and BA0, BA1 are “Don’t Care.”
except for CKE.
delay).
512MB (SR), 1GB (DR): (x64) 168-Pin SDRAM UDIMM
CS#
H
L
L
L
L
L
L
L
L
–
–
13
RAS# CAS# WE# DQMB
H
H
H
H
X
L
L
L
L
–
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
H
H
H
H
L
L
L
L
–
–
X
H
H
H
H
L
L
L
L
–
–
L/H
L/H
X
X
X
X
X
X
X
H
L
Bank/Row
©2002 Micron Technology, Inc. All rights reserved.
Bank/Col
Bank/Col
Op-code
ADDR
Code
X
X
X
X
–
–
High-Z
Active
Active
Commands
Valid
DQ
X
X
X
X
X
X
X
Notes
4, 5
1
2
2
3
6
7
7