MT16HTF12864HY-40EB3 Micron Technology Inc, MT16HTF12864HY-40EB3 Datasheet - Page 10
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MT16HTF12864HY-40EB3
Manufacturer Part Number
MT16HTF12864HY-40EB3
Description
MODULE SDRAM DDR2 1GB 200SODIMM
Manufacturer
Micron Technology Inc
Specifications of MT16HTF12864HY-40EB3
Memory Type
DDR2 SDRAM
Memory Size
1GB
Speed
400MT/s
Package / Case
200-SODIMM
Main Category
DRAM Module
Sub-category
DDR2 SDRAM
Module Type
200SODIMM
Device Core Size
64b
Organization
128Mx64
Total Density
1GByte
Chip Density
512Mb
Access Time (max)
60ps
Maximum Clock Rate
400MHz
Operating Supply Voltage (typ)
1.8V
Operating Current
976mA
Number Of Elements
16
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
200
Mounting
Socket
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Table 11:
PDF: 09005aef818e4054/Source: 09005aef818e40d2
HTF16C128_256x64H.fm - Rev. B 11/06 EN
Parameter/Condition
Operating one bank active-precharge current;
t
commands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current; I
CL = CL (I
t
bus inputs are switching; Data pattern is same as I
Precharge power-down current; All device banks idle;
is LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge quiet standby current; All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data
bus inputs are floating
Precharge standby current; All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
Active power-down current; All device banks open;
t
are stable; Data bus inputs are floating
Active standby current; All device banks open;
MAX (I
Other control and address bus inputs are switching; Data bus inputs are
switching
Operating burst write current; All device banks open, continuous burst
writes; BL = 4, CL = CL (I
=
inputs are switching; Data bus inputs are switching
Operating burst read current; All device banks open, continuous burst
reads, I
MAX (I
Address bus inputs are switching; Data bus inputs are switching
Burst refresh current;
(I
control and address bus inputs are switching; Data bus inputs are switching
Self refresh current; CK and CK# at 0V; CKE ≤ 0.2V; Other control and
address bus inputs are floating; Data bus inputs are floating
Operating bank interleave read current; All device banks interleaving
reads, I
t
HIGH, S# is HIGH between valid commands; Address bus inputs are stable
during deselects; Data bus inputs are switching; See I
RC =
RCD =
CK (I
CK =
DD
t
RP (I
) interval; CKE is HIGH, S# is HIGH between valid commands; Other
DD
t
t
RC (I
CK (I
DD
DD
DD
t
OUT
OUT
); CKE is LOW; Other control and address bus inputs
RCD (I
DD
),
); CKE is HIGH, S# is HIGH between valid commands; Address bus
),
= 0mA; BL = 4, CL = CL (I
DD
t
= 0mA; BL = 4, CL = CL (I
t
DD
), AL = 0;
RP =
RP =
),
DDR2 I
Values shown for DDR2 SDRAM components only
),
DD
t
t
RAS =
RC =
); CKE is HIGH, S# is HIGH between valid commands; Address
t
t
RP(I
RP (I
Notes:
t
t
DD
CK =
DD
DD
RC (I
t
RAS MIN (I
DD
); CKE is HIGH, S# is HIGH between valid commands;
t
); CKE is HIGH, S# is HIGH between valid commands;
CK =
Specifications and Conditions – 2GB (die revision E)
), AL = 0;
DD
t
CK (I
1. Value calculated as one module rank in this operating condition, and all other module ranks in
2. Value calculated reflects all module ranks in this operating condition.
),
t
CK (I
t
I
RRD =
DD
DD
DD
2
t
),
DD
P
CK =
DD
DD
); CKE is HIGH, S# is HIGH between valid
(CKE LOW) mode.
t
RC =
), AL =
), AL = 0;
); Refresh the command at every
t
RRD (I
t
CK (I
t
RC (I
t
RCD (I
DD
DD
t
),
DD
CK =
),
t
t
DD
CK =
t
RCD =
),
RAS =
DD
1GB, 2GB: (x64, DR) 200-Pin DDR2 SDRAM SODIMM
t
CK =
t
t
4W
DD
RAS =
CK =
t
) - 1 ×
CK (I
t
7 conditions for detail
t
CK =
CK (I
t
t
t
t
RCD (I
RAS MAX (I
OUT
CK =
CK (I
t
DD
t
CK (I
t
CK =
10
RAS MIN (I
t
DD
CK (I
),
= 0mA; BL = 4,
DD
t
Fast PDN Exit
MR[12] = 0
Slow PDN Exit
MR[12] = 1
),
t
DD
CK (I
DD
RAS =
t
t
),
DD
CK (I
RAS =
); CKE is
); CKE is
);
DD
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
t
DD
); CKE
RAS
t
),
t
RFC
);
RAS
),
t
RP
Symbol
I
I
I
I
I
I
I
DD
DD
DD
DD
DD
I
I
DD
DD
I
I
I
DD
DD
DD
DD
DD
4W
2Q
2N
3N
4R
2P
3P
0
1
5
6
7
1
1
2
2
1
2
2
1
2
2
2
1
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-800 -667 -53E -40E Units
Electrical Specifications
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©2004 Micron Technology, Inc. All rights reserved.
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mA
mA
mA
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mA
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