MT18LSDT6472G-133D2 Micron Technology Inc, MT18LSDT6472G-133D2 Datasheet - Page 3

• Manufacturer Part Number: MT18LSDT6472G-133D2
• Description: MODULE SDRAM 512MB 168DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18LSDT6472G-133D2

• Memory Type: SDRAM
• Memory Size: 512MB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 256Mb
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 2.43A
• Number Of Elements: 18
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 6:
Pin numbers are listed in module pinout order; see pin assignment tables on page 2 for more information
16,32,Meg x 64 DDR SDRAM DIMMs (Footer Desc variable)
SD18C16_32_64x72G_B.fm - Rev. B 1/03 EN
104, 139-142, 144, 149-151,
28-29, 46-47, 112-113, 130-
58, 60, 65-67, 69-72, 74-77,
2-5, 7-11, 13-17, 19-20, 55-
86-89, 91-95, 97-101, 103-
21-22, 52-53, 105-106,
33–38, 117–121, 123,
153-156, 158-161
42, 79, 125, 163
PIN NUMBERS
126
27, 111, 115
165-167
136-137
39, 122
30, 45
(512MB)
128
131
147
81
83
Pin Descriptions
WE#, CAS#, RAS#
DQMB0- DQMB7
(128MB/ 256MB)
DQ0-DQ63
SYMBOL
BA0, BA1
CK0-CK3
S0#, S2#
(512MB)
SA0-SA2
CB0-CB7
A0-A11
A0-A12
CKE0
REGE
SCL
WP
Output
Output
Input/
Input/
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
168-PIN REGISTERED SDRAM DIMM
3
Command Inputs: WE#, CAS#, and RAS# (along with S0#, S2#)
define the command being entered.
Clock: CK0 is distributed through an on-board PLL to all
devices. CK1-CK3 are terminated.
Clock Enable: CKE0 activates (HIGH) and deactivates (LOW)
the CK0 signal. Deactivating the clock provides POWER-
DOWN and SELF REFRESH operation (all device banks idle) or
CLOCK SUSPEND operation (burst access in progress). CKE0 is
synchronous except after the device enters power-down and
self refresh modes, where CKE0 becomes asynchronous until
after exiting the same mode. The input buffers, including
CK0, are disabled during power-down and self refresh
modes, providing low standby power.
Chip Select: S0#, S2# enable (registered LOW) and disable
(registered HIGH) the command decoder. All commands are
masked when S0#, S2# are registered HIGH. S0#, S2# are
considered part of the command code.
Input/Output Mask: DQMB is an input mask signal for write
accesses and an output enable signal for read accesses. Input
data is masked when DQMB is sampled HIGH during a WRITE
cycle. The output buffers are placed in a High-Z state (two-
clock latency) when DQMB is sampled HIGH during a READ
cycle.
Bank Address: BA0 and BA1 define to which device bank the
ACTIVE, READ, WRITE or PRECHARGE command is being
applied.
Address Inputs: A0-A11 (128MB/256MB) or A0-A12 (512MB)
are sampled during the ACTIVE command (device row-
address A0-A11/12) and READ/WRITE command (device
column-address A0-A9 (128MB) or A0- A9/A11 (256MB/
512MB), with A10 defining auto precharge) to select one
location out of the memory array in the respective device
bank. A10 is sampled during a PRECHARGE command to
determine if both device banks are to precharged (A10
HIGH). The address inputs also provide the op-code during a
LOAD MODE REGISTER command.
Write Protect: Serial presence-detect hardware write protect.
Serial Clock for Presence-Detect: SCL is used to synchronize
the presence-detect data transfer to and from the module.
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Register Enable.
Data I/Os: Data bus.
Check Bits.
128MB, 256MB, 512MB (x72, ECC)
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DESCRIPTION
©2003, Micron Technology Inc.