MT18LSDT6472G-133D2 Micron Technology Inc, MT18LSDT6472G-133D2 Datasheet - Page 15

• Manufacturer Part Number: MT18LSDT6472G-133D2
• Description: MODULE SDRAM 512MB 168DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18LSDT6472G-133D2

• Memory Type: SDRAM
• Memory Size: 512MB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 512MByte
• Chip Density: 256Mb
• Access Time (max): 6/5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 2.43A
• Number Of Elements: 18
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Notes
16,32,Meg x 64 DDR SDRAM DIMMs (Footer Desc variable)
SD18C16_32_64x72G_B.fm - Rev. B 1/03 EN
10.
11. AC timing and Idd tests have V
12. Other input signals are allowed to transition no
13. I
14. Timing actually specified by
15. Timing actually specified by
3. I
6. An initial pause of 100µs is required after power-
7. AC characteristics assume
8. In addition to meeting the transition rate specifi-
1. All voltages referenced to V
2. This parameter is sampled. V
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to
9. Outputs measured at 1.5V with equivalent load:
= 1 MHz, T
rates. Specified values are obtained with mini-
mum cycle time and the outputs open.
indicate cycle time at which proper operation
over the full temperature range is ensured; (0°C £
T
up, followed by two AUTO Refresh commands,
before proper device operation is ensured. (V
and V
V
AUTO Refresh command wake-ups should be
repeated any time the tREF refresh requirement is
exceeded.
cation, the clock and CKE must transit between
V
tonic manner.
t
the open circuit condition; it is not a reference to
V
t
with timing referenced to 1.5V crossover point. If
the input transition time is longer than 1 ns, then
the timing is referenced at V
(MIN) and no longer at the 1.5V crossover point.
more than once every two clocks and are other-
wise at valid V
properly initialized.
fied as a reference only at minimum cycle rate.
specified as a reference only at minimum cycle
rate.
HZ defines the time at which the output achieves
OH before going High-Z.
DD
DD
A
OH
SS
IH
£ +70°C).
and V
and V
is dependent on output loading and cycle
specifications are tested after the device is
or V
DD
OL
Q must be powered up simultaneously.
SS
IL
A
. The last valid data element will meet
Q must be at same potential.) The two
= 25°C; pin under test biased at 1.4V.
(or between V
IH
or V
Q
IL
levels.
t
IL
SS
T = 1ns.
t
.
50pF
and V
WR plus
DD
t
CKS; clock(s) speci-
IL
IL
, VV
= 0V and V
(MAX) and V
IH
DD
)
t
RP; clock(s)
Q = +3.3V; f
IN
a mono-
IH
= 3V,
DD
IH
168-PIN REGISTERED SDRAM DIMM
15
128MB, 256MB, 512MB (x72, ECC)
16. Timing actually specified by
17. Required clocks are specified by JEDEC function-
18. The Idd current will increase or decrease propor-
19. Address transitions average one transition every
20. CLK must be toggled a minimum of two times
21. Based on
22. Vih overshoot: V
23. The clock frequency must remain constant (stable
24. Auto precharge mode only. The precharge timing
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27.
28. Parameter guaranteed by design.
29. The value of
30. For -10E, CL= 2 and tCK = 10ns; for -133, CL = 3
31. CKE is HIGH during refresh command period
32. This AC timing function will show an extra clock
33. Leakage number reflects the worst case leakage
ality and are not dependent on any timing param-
eter.
tionally according to the amount of frequency
alteration for the test condition.
two clocks.
during this period.
133 and -13E.
width £ 3ns, and the pulse width cannot be
greater than one third of the cycle rate. V
shoot: V
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during
access or precharge states (READ, WRITE, includ-
ing
be used to reduce the data rate.
budget (
and 7ns for -10E after the first clock delay, after
the last WRITE is executed. May not exceed limit
set for precharge mode.
t
and is guaranteed by design.
SPDs is calculated from
and
t
actually a nominal value and does not result in a
fail value.
cycle when in registered mode.
possible through the module pin, not what each
memory device contributes.
AC for -133/-13E at CL = 3 with no load is 4.6ns
RFC (MIN) else CKE is LOW. The I
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
WR, and PRECHARGE commands). CKE may
t
CK = 7.5ns; for -13E, CL = 2 and
IL
t
RP) begins 7ns for -13E; 7.5ns for -133
t
CK = 10ns for -10E, and
(MIN) = -2V for a pulse width £ 3ns.
t
RAS. use in -13E speed grade module
IH
(MAX) = V
t
RC -
t
WR.
DD
t
RP = 45ns.
Q + 2V for a pulse
©2003, Micron Technology Inc.
t
CK = 7.5ns for -
t
CK = 7.5ns.
DD
6 limit is
IL
under-