MT16LSDT6464AY-13ED2 Micron Technology Inc, MT16LSDT6464AY-13ED2 Datasheet - Page 19

• Manufacturer Part Number: MT16LSDT6464AY-13ED2
• Description: MODULE SDRAM 512MB 168-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16LSDT6464AY-13ED2

• Memory Type: SDRAM
• Memory Size: 512MB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168UDIMM
• Device Core Size: 64b
• Organization: 64Mx64
• Total Density: 512MByte
• Chip Density: 256Mb
• Access Time (max): 5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 1.096A
• Number Of Elements: 16
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Notes
PDF: 09005aef807b3771/Source: 09005aef807b37b5
SD8_16C32_64x64AG.fm - Rev. D 3/05 EN
10.
11. AC timing and I
12. Other input signals are allowed to transition no more than once every two clocks and
13. I
14. Timing actually specified by
15. Timing actually specified by
16. Timing actually specified by
17. Required clocks are specified by JEDEC functionality and are not dependent on any
18. The I
19. Address transitions average one transition every two clocks.
20. CLK must be toggled a minimum of two times during this period.
21. Based on
22. V
1. All voltages referenced to V
2. This parameter is sampled. V
3. I
4. Enables on-chip refresh and address counters.
5. The minimum specifications are used only to indicate cycle time at which proper
7. AC characteristics assume
8. In addition to meeting the transition rate specification, the clock and CKE must tran-
9. Outputs measured at 1.5V with equivalent load:
6. An initial pause of 100µs is required after power-up, followed by two AUTO REFRESH com-
1.4; f = 1 MHz.
with minimum cycle time and the outputs open.
operation over the full temperature range is ensured (Commercial Temperature: 0°C ≤
T
mands, before proper device operation is ensured. (V
simultaneously. V
mand wake-ups should be repeated any time the tREF refresh requirement is exceeded.
sit between V
Q
t
a reference to V
High-Z.
crossover point. If the input transition time is longer than 1ns, then the timing is ref-
erenced at V
are otherwise at valid V
cycle rate.
minimum cycle rate.
timing parameter.
frequency alteration for the test condition.
cannot be greater than one third of the cycle rate. V
a pulse width ≤ 3ns.
DD
HZ defines the time at which the output achieves the open circuit condition; it is not
DD
A
IH
+70°C and Industrial Temperature: -40°C ≤ Τ
specifications are tested after the device is properly initialized.
overshoot: V
is dependent on output loading and cycle rates. Specified values are obtained
DD
50pF
current will increase or decrease proportionally according to the amount of
t
256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM
CK = 10ns for -10E, and
IL
IH
(MAX) and V
and V
OH
SS
DD
IH
and V
(MAX) = V
or V
tests have V
IL
IH
(or between V
OL
SSQ
or V
. The last valid data element will meet
t
19
SS
T = 1ns.
IH
t
must be at same potential.) The two AUTO REFRESH com-
.
t
WR.
CKS; clock(s) specified as a reference only at minimum
(MIN) and no longer at the 1.5V crossover point.
t
DD
IL
DDQ
WR plus
levels.
IL
, V
t
CK = 7.5ns for -133 and -13E.
= 0V and V
+ 2V for a pulse width ≤ 3ns, and the pulse width
DDQ
Micron Technology, Inc., reserves the right to change products or specifications without notice.
IL
t
and V
= +3.3V; T
RP; clock(s) specified as a reference only at
IH
IH
Α
) in a monotonic manner.
= 3V, with timing referenced to 1.5V
≤ +85°C).
A
IL
DD
= 25°C; pin under test biased at
undershoot: V
and V
©2003 Micron Technology, Inc. All rights reserved.
DDQ
must be powered up
t
IL
OH before going
(MIN) = -2V for
Notes