MT16LSDT6464AY-13ED2 Micron Technology Inc, MT16LSDT6464AY-13ED2 Datasheet
MT16LSDT6464AY-13ED2
Specifications of MT16LSDT6464AY-13ED2
Related parts for MT16LSDT6464AY-13ED2
MT16LSDT6464AY-13ED2 Summary of contents
Page 1
... PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN Products and specifications discussed herein are subject to change by Micron without notice. 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM ® Web site: www.micron.com/products/modules Figure 1: Low Profile 1.125in. (28.575mm) Options • Package 168-pin DIMM (standard) 168-pin DIMM (lead-free) • ...
Page 2
... MT8LSDT3264AY-10E_ MT16LSDT6464AAG-13E_ MT16LSDT6464AY-13E_ MT16LSDT6464A(I)G-133_ MT16LSDT6464A(I)Y-133_ MT16LSDT6464AG-10E_ MT16LSDT6464AY-10E_ Note: The designators for component and PCB revision are the last two characters of each part number. Consult factory for current revision codes. Example: MT8LSDT3264AG-133D2. Pin Assignments and Descriptions Table 4: Pin Assignment (168-Pin DIMM Front) ...
Page 3
Table 5: Pin Assignment (168-Pin DIMM Back) Pin 100 101 102 103 104 105 Figure 2: Pin Locations (168-Pin DIMM) Front View U1 U2 PIN ...
Page 4
Table 6: Pin Descriptions Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 2 for for information Pin Number 27, 111, 115 RAS#, CAS#, 42, 79, 125, 163 63, 128 CKE0, CKE1 30, 45,114, 129 ...
Page 5
... Type Description V Supply Power Supply: +3.3V ±0.3V Supply Ground – Not Connected: These pins are not connected on these modules. 5 Pin Assignments and Descriptions Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. ...
Page 6
... Functional Block Diagram All resistor values are 10Ω unless otherwise specified. Per industry standard, Micron modules use various component speed grades as refer- enced in the module part numbering guide at: www.micron.com/numberguide. Standard modules use the following SDRAM device: MT48LC32M8A2TG; Lead-free modules use the following SDRAM device: MT48LC32M8A2P. Contact Micron for Indus- trial Temp ...
Page 7
Figure 4: Dual Rank S0# DQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 S2# DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 ...
Page 8
... READ or WRITE command are used to select the starting column location for the burst access. The modules provide for programmable READ or WRITE burst lengths locations, or the full page, with a burst terminate option. An AUTO PRECHARGE func- tion may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence ...
Page 9
SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND INHIBIT or NOP . Starting at some point during this 100µs period and continuing at least through the end of this period, Command Inhibit or NOP ...
Page 10
Figure 5: Mode Register Definition Diagram *Should program M12, M11, M10 = “0, 0, 0” to ensure compatibility with future devices. PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM A12 ...
Page 11
Table 7: Burst Definitions Burst Length Full Page Notes: 1. For full-page accesses 1,024 2. For a burst length of two, A1–A9 select the block of two burst; A0 selects the starting col- umn within the block. 3. ...
Page 12
Figure 6: CAS Latency Diagram CLK COMMAND DQ CLK COMMAND DQ Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit ...
Page 13
Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. Write Burst Mode When the burst length programmed via M0–M2 applies to both READ and WRITE bursts; when ...
Page 14
Electrical Specifications Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of ...
Page 15
Table 13: I Specifications and Conditions – 256MB DD Notes 11, 13; notes appear on page 19; V Parameter/Condition OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE (MIN) STANDBY CURRENT: ...
Page 16
Table 15: Capacitance – 256MB Note 2; notes appear on page 19 Parameter Input Capacitance: Address and Command Input Capacitance: CK0 Input Capacitance: CK2 Input Capacitance: S0# Input Capacitance: S2# Input Capacitance: CKE Input Capacitance: DQMB0, 2– ...
Page 17
Table 17: Electrical Characteristics and Recommended AC Operating Conditions Notes 11, 22; notes appear on page 19 Module AC timing parameters comply with PC100 and PC133 Design Specs, based on component parameters AC Characteristics Parameter Access ...
Page 18
Table 18 Functional Characteristics Notes 11, 22; notes appear on page 19 Parameter READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit ...
Page 19
Notes 1. All voltages referenced This parameter is sampled MHz with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications ...
Page 20
The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including used to reduce the data rate. 24. Auto precharge ...
Page 21
Serial Presence-Detect SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 7, Data Validity, ...
Page 22
Figure 8: Definition of Start and Stop SCL SDA Figure 9: Acknowledge Response From Receiver SCL from Master Data Output from Transmitter Data Output from Receiver PDF: 09005aef807b3771/Source: 09005aef807b37b5 SD8_16C32_64x64AG.fm - Rev. D 3/05 EN 256MB (x64, SR), 512MB (x64, ...
Page 23
Table 19: EEPROM Device Select Code The most significant bit (b7) is sent first Memory Area Select Code (two arrays) Protection Register Select Code Table 20: EEPROM Operating Modes Mode RW Bit Current Address Read RandomAddressRead Sequential Read Byte Write ...
Page 24
Table 21: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V Parameter/Condition SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA OUT INPUT LEAKAGE CURRENT: ...
Page 25
Table 23: Serial Presence-Detect Matrix V = +3.3V ±0.3V; “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” DD Byte Description 0 Number of Bytes Used by Micron 1 Total Number of SPD Memory Bytes 2 Memory Type 3 Number of ...
Page 26
... RC 66ns (-133) 70ns (10E) REV. 1.2 (-13E) (-133) (-10E) MICRON 0 100 MHz (-13E/ -133/-10E) t RAS used for -13E modules is calculated from Micron Technology, Inc., reserves the right to change products or specifications without notice. 26 Serial Presence-Detect MT8LSDT3264A MT16LSDT6464A ...
Page 27
Module Dimensions All dimensions are in inches (millimeters); Figure 11: 168-Pin Single Rank Module 0.079 (2.00) R (2X 0.118 (3.00) (2X) 0.118 (3.00) TYP 0.118 (3.00) TYP 2.625 (66.68) PIN 1 (PIN 85 ON BACKSIDE) PDF: 09005aef807b3771/Source: 09005aef807b37b5 ...
Page 28
Figure 12: 168-Pin Dual Rank Module 0.079 (2.00) R (2X 0.118 (3.00) (2X) 0.118 (3.00) TYP 0.118 (3.00) TYP 2.625 (66.68) PIN 1 U11 U12 PIN 168 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: ...