MT16LSDT6464AY-13ED2 Micron Technology Inc, MT16LSDT6464AY-13ED2 Datasheet - Page 12

• Manufacturer Part Number: MT16LSDT6464AY-13ED2
• Description: MODULE SDRAM 512MB 168-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT16LSDT6464AY-13ED2

• Memory Type: SDRAM
• Memory Size: 512MB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168UDIMM
• Device Core Size: 64b
• Organization: 64Mx64
• Total Density: 512MByte
• Chip Density: 256Mb
• Access Time (max): 5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 1.096A
• Number Of Elements: 16
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 6:
Burst Type
CAS Latency
Operating Mode
PDF: 09005aef807b3771/Source: 09005aef807b37b5
SD8_16C32_64x64AG.fm - Rev. D 3/05 EN
CAS Latency Diagram
COMMAND
COMMAND
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of the accesses within a burst is determined by the burst length, the burst
type, and the starting column adress, as shown in Table 7, Burst Definitions, .
The CAS latency is the delay, in clock cycles, between the registration of a READ com-
mand and the availability of the first piece of output data. The latency can be set to two
or three clocks.
If a READ command is registered at clock edge n, and the latency is m clocks, the data
will be available by clock edge n + m. The DQs will start driving as a result of the clock
edge one cycle earlier (n + m - 1), and provided that the relevant access times are met,
the data will be valid by clock edge n + m. For example, assuming that the clock cycle
time is such that all relevant access times are met, if a READ command is registered at T0
and the latency is programmed to two clocks, the DQs will start driving after T1 and the
data will be valid by T2, as shown in Figure 6, CAS Latency Diagram. Table 8, CAS
Latency Table, indicates the operating frequencies at which each CAS latency setting
can be used.
Reserved states should not be used as unknown operation or incompatibility with future
versions may result.
The normal operating mode is selected by setting M7 and M8 to zero; the other combi-
nations of values for M7 and M8 are reserved for future use and/or test modes. The pro-
grammed burst length applies to both READ and WRITE bursts.
CLK
CLK
DQ
DQ
READ
READ
256MB (x64, SR), 512MB (x64, DR) 168-Pin SDRAM UDIMM
T0
T0
CAS Latency = 2
NOP
NOP
T1
T1
t
t AC
LZ
CAS Latency = 3
12
T2
NOP
T2
NOP
t
t AC
LZ
D
t OH
OUT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
T3
T3
NOP
D
t OH
OUT
DON’T CARE
UNDEFINED
Mode Register Definition
T4
©2003 Micron Technology, Inc. All rights reserved.