MT8VDDT6432UY-5K1 Micron Technology Inc, MT8VDDT6432UY-5K1 Datasheet - Page 27

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MT8VDDT6432UY-5K1

Manufacturer Part Number
MT8VDDT6432UY-5K1
Description
MODULE DDR 256MB 100-DIMM
Manufacturer
Micron Technology Inc
Datasheet

Specifications of MT8VDDT6432UY-5K1

Memory Type
DDR SDRAM
Memory Size
256MB
Speed
400MT/s
Package / Case
100-DIMM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Figure 9:
pdf: 09005aef80745603, source: 09005aef807455eb
DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN
Pull-Up Characteristics
41. For the -6 and -75 I
42. Random addressing changing and 50 percent of data changing at every transfer.
43. Random addressing changing and 100 percent of data at every transfer.
44. CKE must be active (high) during the entire time a refresh command is executed.
45. I
46. Whenever the operating frequency is altered, not including jitter, the DLL is required
47. Leakage number reflects the worst case leakage possible through the module pin, not
48. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or
49. The -6 speed grade will operate with
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until
is similar to I
stable. Although I
to be reset. This is followed by 200 clock cycles.
what each memory device contributes.
LOW.
any slower frequency.
DD
2N specifies the DQ and DQS to be driven to a valid high or low logic level. I
DD
128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM
2F except I
DD
DD
2F, I
3N is specified to be 35mA per DDR SDRAM device at 100 MHz.
DD
27
2N, and I
DD
2Q specifies the address and control inputs to remain
DD
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
RAS (MIN) = 40ns and
t
REF later.
2Q are similar, I
DD
©2004, 2005 Micron Technology, Inc. All rights reserved.
2F is “worst case.”
t
RAS (MAX) = 120,000ns at
Notes
DD
2Q

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