MT8VDDT6432UY-5K1 Micron Technology Inc, MT8VDDT6432UY-5K1 Datasheet
MT8VDDT6432UY-5K1
Specifications of MT8VDDT6432UY-5K1
Related parts for MT8VDDT6432UY-5K1
MT8VDDT6432UY-5K1 Summary of contents
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DDR SDRAM Unbuffered DIMM MT8VDDT3232U – 128MB MT8VDDT6432U – 256MB MT8VDDT12832U – For DDR SDRAM component specifications, please refer to the Micron Features • 100-pin, dual in-line memory module (DIMM) • Fast data transfer rate: PC2100 and PC2700 • Utilizes ...
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... MT8VDDT3232UG-75Z__ MT8VDDT3232UY-75Z__ MT8VDDT3232UG-75__ MT8VDDT3232UY-75__ MT8VDDT6432UG-6__ MT8VDDT6432UY-6__ MT8VDDT6432UG-75Z__ MT8VDDT6432UY-75Z__ MT8VDDT6432UG-75__ MT8VDDT6432UY-75__ MT8VDDT12832UG-6__ MT8VDDT12832UY-6__ MT8VDDT12832UG-75Z__ MT8VDDT12832UY-75Z__ MT8VDDT12832UG-75__ MT8VDDT12832UY-75__ All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT8VDDT3232UG-75B1. pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_1 ...
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Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of Figures Figure 1: 100-Pin DIMM (MO-161 ...
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... I Specifications and Conditions – 256MB .19 DD Table 13: I Specifications and Conditions – 512MB .20 DD Table 14: Capacitance (All Modules .21 Table 15: Component Electrical Characteristics and Recommended AC Operating Conditions . . . . . . . . . . . .21 Table 16: EEPROM Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Table 17: EEPROM Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Table 18: Serial Presence-Detect EEPROM DC Operating Conditions .33 Table 19: Serial Presence-Detect EEPROM AC Operating Conditions ...
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... DQS1 DQ10 38 Note: Pin Connect for the 128MB module, or A12 for the 256MB or 512MB modules. Figure 2: Module Layout Front View U1 U2 PIN 1 PIN 23 pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM Symbol Pin Symbol Pin ...
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Table 4: Pin Descriptions Pin numbers may not correlate with symbols; refer to Figure 3 on page 6 for more information Pin Numbers 32, 79, 81 WE#, CAS#, RAS# 17, 18, 67, 68 CK0, CK0#, CK1, CK1# 20, 70 CKE0, ...
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... Power Supply: +2.5V ±0.2V Supply Ground. SS DNU — Do Not Use: This pin is not connected on these modules, but is an assigned pin on other modules in this product family. NC — No Connect: These pins should be left unconnected. 8 Pin Assignments and Descriptions Description Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... Functional Block All resistor values are 22Ω unless otherwise specified. Per industry standard, Micron modules utilize various component speed grades, as referenced in the module part number guide at www.micron.com/numberguide. Standard modules use the following DDR SDRAM devices: MT46V16M8TG (128MB); MT46V32M8TG (256MB); and MT46V64M8TG (512MB). Lead-free modules use the fol- lowing DDR SDRAM devices: MT46V16M8P (128MB) ...
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... Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to DDR SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence ...
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DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. Mode Register Definition The mode ...
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If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge The CAS Latency Table indicates the operating frequencies at which each ...
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Table 5: Burst Definition Table Burst Length Notes: 1. For a burst length of two, A1–Ai select the two-data-element block; A0 selects the first access within the block. 2. For a burst length of four, A2–Ai select the four-data-element block; ...
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Figure 5: CAS Latency Diagram COMMAND COMMAND Operating Mode The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7–A11 (128MB, 256MB), or A7–A12 (512MB) each set to zero, and bits A0–A6 set to the ...
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... DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles with CKE HIGH must occur before a READ command can be issued. Figure 6: Extended Mode Register Definition Diagram 128MB Module Address Bus BA1 BA0 256MB and 512MB Modules Address Bus BA1 BA0 E11 ...
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Commands Table 7, Commands Truth Table, and Table 8, DM Operation Truth Table, provide a gen- eral reference of available commands. For a more detailed description of commands and operations, refer to the 128Mb, 256Mb, or 512Mb DDR SDRAM component ...
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Parameter Tables Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the ...
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Table 11: I Specifications and Conditions – 128MB DD DDR SDRAM components only Notes: 1–5, 14, 48; notes appear on pages 23–27; 0°C ≤ T Parameter/Condition OPERATING CURRENT: One device bank; Active-Precharge (MIN); ...
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Table 12: I Specifications and Conditions – 256MB DD DDR SDRAM components only Notes: 1–5, 14, 48; notes appear on pages 23–27; 0°C ≤ T Parameter/Condition OPERATING CURRENT: One device bank; Active-Precharge (MIN); ...
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Table 13: I Specifications and Conditions – 512MB DD DDR SDRAM components only Notes: 1–5, 14, 48; notes appear on pages 23–27; 0°C ≤ T Parameter/Condition OPERATING CURRENT: One device bank; Active-Precharge (MIN); ...
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... Table 14: Capacitance (All Modules) Note: 11; notes appear on pages 23–27 Parameter Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address Input Capacitance: S#; CK/CK#; CKE Table 15: Component Electrical Characteristics and Recommended AC Operating Conditions Notes: 1–5, 12–15, 29, 48; notes appear on pages 23–27; 0°C ≤ Characteristics ...
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Table 15: Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) AC Characteristics Parameter ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble ...
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Notes 1. All voltages referenced Tests for AC timing nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: 4. ...
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HZ and tions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 17. The intent of the “Don’t Care” state after completion ...
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Figure 7: Derating Data Valid Window 3.8 3.750 3.700 3.6 3.650 3.4 3.2 t -75/-75Z @ CK = 10ns 3.0 t -75/-75Z @ CK = 7.5ns 6ns N/A 2.8 2.6 2.500 2.463 2.4 2.2 2.0 ...
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The full variation in the ratio of the maximum to minimum pull-up and pull- f. The full variation in the ratio of the nominal pull-up to pull-down current should 34. The voltage levels used are derived from a minimum ...
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Figure 9: Pull-Up Characteristics 41. For the -6 and -75 I 42. Random addressing changing and 50 percent of data changing at every transfer. 43. Random addressing changing and 100 percent of data at every transfer. 44. CKE must be ...
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Initialization To ensure device operation the DRAM must be initialized as described below: 1. Simultaneously apply power Apply V 3. Assert and hold CKE at a LVCMOS logic low. 4. Provide stable CLOCK signals. 5. Wait at ...
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Figure 10: Initialization Flow Diagram Step pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 128MB, 256MB, 512MB: ...
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Serial Presence Detect SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 11, Data ...
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Figure 12: Definition of Start and Stop SCL SDA Figure 13: Acknowledge Response From Receiver SCL from Master Data Output from Transmitter Data Output from Receiver pdf: 09005aef80745603, source: 09005aef807455eb DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN 128MB, 256MB, 512MB: (x32, ...
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Table 16: EEPROM Device Select Code The most significant bit (b7) is sent first Memory Area Select Code (two arrays) Protection Register Select Code Table 17: EEPROM Operating Modes Mode RW Bit 1 Current Address Read 0 Random Address Read ...
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Table 18: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V Parameter/condition SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA OUT INPUT LEAKAGE CURRENT: ...
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Table 20: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 35 Byte Description 0 Number of SPD Bytes Used by Micron 1 Total Number of Bytes in SPD Device 2 Fundamental Memory Type ...
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... RFC t CK 12ns (-6) MAX 13ns (-75Z/-75) 0.45ns (-6) 0.5ns (-75Z/-75) 0.55ns (-6) 0.75ns (-75Z/-75) Release 1.0 -6 -75Z -75 MICRON (Continued) 01–12 1 RAS used for -75 modules is calculated from RP, RCD and RAP for -335 modules indicated as 18ns to align with industry 35 Serial Presence Detect MT8VDDT3232U MT8VDDT6432U MT8VDDT12832U ...
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Module Dimensions All dimensions are in inches (millimeters); Figure 15: 100-Pin DIMM Dimensions 0.079 (2.00) R (2X) U1 0.118 (3.0) DIA (2X) 0.118 (3.0) TYP PIN 1 0.039 (1.0) TYP U6 0.084 (2.13) TYP PIN 100 0.118 (3.0) TYP Data ...