MT8VDDT6432UY-5K1 Micron Technology Inc, MT8VDDT6432UY-5K1 Datasheet - Page 11

• Manufacturer Part Number: MT8VDDT6432UY-5K1
• Description: MODULE DDR 256MB 100-DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT8VDDT6432UY-5K1

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 400MT/s
• Package / Case: 100-DIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Mode Register Definition
Burst Length
Burst Type
Read Latency
pdf: 09005aef80745603, source: 09005aef807455eb
DD8C32_64_128x32UG_2.fm - Rev. G 5/05 EN
bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on
the module, permanently disabling hardware write protect.
The mode register is used to define the specific mode of operation of DDR SDRAM
devices. This definition includes the selection of a burst length, a burst type, a CAS
latency and an operating mode, as shown in Figure 4, Mode Register Definition Dia-
gram, on page 12. The mode register is programmed via the MODE REGISTER SET com-
mand (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is
programmed again or the device loses power (except for bit A8, which is self-clearing).
Reprogramming the mode register will not alter the contents of the memory, provided it
is performed correctly. The mode register must be loaded (reloaded) when all device
banks are idle and no bursts are in progress, and the controller must wait the specified
time before initiating the subsequent operation. Violating either of these requirements
will result in unspecified operation.
Mode register bits A0–A2 specify the burst length, A3 specifies the type of burst (sequen-
tial or interleaved), A4–A6 specify the CAS latency, and A7–A11 (128MB, 256MB) or A7–
A12 (512MB) specify the operating mode.
Read and write accesses to DDR SDRAM devices are burst oriented, with the burst
length being programmable, as shown in Figure 4, Mode Register Definition Diagram.
The burst length determines the maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are
available for both the sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation or incompatibility with
future versions may result.
When a READ or WRITE command is issued, a block of columns equal to the burst
length is effectively selected. All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a boundary is reached. The block is
uniquely selected by A1–A9 (128MB, 256MB) or A1–A9, A11 (512MB) when the burst
length is set to two, by A2–A9 (128MB, 256MB) or A2–A9, A11 (512MB) when the burst
length is set to four and by A3–A9 (128MB, 256MB) or A3–A9, A11 ( 512MB) when the
burst length is set to eight. The remaining (least significant) address bit(s) is (are) used
to select the starting location within the block. The programmed burst length applies to
both READ and WRITE bursts.
Accesses within a given burst may be programmed to be either sequential or interleaved;
this is referred to as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type
and the starting column address, as shown in Table 5, Burst Definition Table, on page 13.
The READ latency is the delay, in clock cycles, between the registration of a READ com-
mand and the availability of the first bit of output data. The latency can be set to 2 or 2.5
clocks, as shown in Figure 5, CAS Latency Diagram, on page 14.
128MB, 256MB, 512MB: (x32, DR) 100-Pin DDR UDIMM
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
Mode Register Definition
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