MT4VDDT3264HY-335F2 Micron Technology Inc, MT4VDDT3264HY-335F2 Datasheet - Page 27

• Manufacturer Part Number: MT4VDDT3264HY-335F2
• Description: MODULE DDR 256MB 200-SODIMM
• Manufacturer: Micron Technology Inc

Specifications of MT4VDDT3264HY-335F2

• Memory Type: DDR SDRAM
• Memory Size: 256MB
• Speed: 333MT/s
• Package / Case: 200-SODIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 200SODIMM
• Device Core Size: 64b
• Organization: 32Mx64
• Total Density: 256MByte
• Chip Density: 512Mb
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Operating Current: 780mA
• Number Of Elements: 4
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 200
• Mounting: Socket
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1231; MT4VDDT3264HY-335F2

Table 21: Serial Presence-Detect Matrix
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 28
pdf: 09005aef8086ea3d, source: 09005aef8086ea0b
DD4C8_16_32x64HG.fm - Rev. C 9/04 EN
BYTE
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
0
1
2
3
4
5
6
7
8
9
Number of SPD Bytes Used By Micron
Total Number of Bytes In SPD Device
Fundamental Memory Type
Number of Row Addresses on
Assembly
Number of Column Addresses on
Assembly
Number of Physical Ranks on DIMM
Module Data Width
Module Data Width (Continued)
Module Voltage Interface Levels
(V
SDRAM Cycle Time,
= 2.5 (see note 1)
SDRAM Access From Clock,
Latency = 2.5
Module Configuration Type
Refresh Rate/Type
SDRAM Device Width (Primary DDR
SDRAM)
Error-checking DDR SDRAM Data
Width
Minimum Clock Delay, Back-to-Back
Random Column Access
Burst Lengths Supported
Number of Banks on DDR SDRAM
Device
CAS Latencies Supported
CS Latency
WE Latency
SDRAM Module Attributes
SDRAM Device Attributes: General
SDRAM Cycle Time,
= 2
SDRAM Access From Clock,
Latency = 2
SDRAM Cycle Time,
= 1.5
SDRAM Access from CK,
Latency = 1.5
Minimum Row Precharge Time,
(see note 4)
Minimum Row Active to Row Active,
(
Minimum RAS# to CAS# Delay,
(see note 4)
t
RRD)
DD
Q)
DESCRIPTION
t
t
t
CK, CAS Latency
CK, CAS Latency
CK, CAS Latency
t
AC, CAS
t
t
AC, CAS
AC, CAS
t
RCD
t
RP
0.75ns (-262/-26A/-265)
0.75ns (-262/-26A/-265)
Unbuffered/Diff. Clock
7.5ns (-335/-262/-26A)
15ns (-262/-26A/-265)
ENTRY (VERSION)
15.62µs, 7.8µs/SELF
Fast/Concurrent AP
20ns (-26A/-265)
20ns (-26A/-265)
7ns (-262/-26A)
DDR SDRAM
7.5ns (-265)
0.7ns (-335)
0.7ns (-335)
10ns (-265)
18ns (-335)
15ns (-262)
12ns (-335)
18ns (-335)
15ns (-262)
6ns (-335)
SSTL 2.5V
1 clock
2, 4, 8
12,13
None
None
2, 2.5
9, 10
N/A
N/A
128
256
64
16
1
0
4
0
1
27
64MB, 128MB, 256MB (x64, SR)
200-PIN DDR SDRAM SODIMM
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MT4VDDT864H MT4VDDT1664H MT4VDDT3264H
A0
80
08
07
0C
09
01
40
00
04
60
70
75
70
75
00
80
10
00
01
0E
04
0C
01
02
20
C1
75
70
75
00
00
48
3C
50
30
3C
48
3C
50
©2004 Micron Technology, Inc. All rights reserved.
0D
A0
80
08
09
01
40
00
04
60
70
75
70
75
00
82
10
00
01
0E
04
0C
01
02
20
C1
75
70
75
00
00
48
3C
50
30
3C
48
3C
50
07
0D
0A
A0
0C
C1
3C
3C
3C
80
08
07
01
40
00
04
60
70
75
70
75
00
82
10
00
01
0E
04
01
02
20
75
70
75
00
00
48
50
30
48
50