MT4VDDT3264HY-335F2 Micron Technology Inc, MT4VDDT3264HY-335F2 Datasheet
MT4VDDT3264HY-335F2
Specifications of MT4VDDT3264HY-335F2
MT4VDDT3264HY-335F2
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MT4VDDT3264HY-335F2 Summary of contents
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... PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 128MB, 256MB (x64, SR) PC3200 200-PIN DDR SDRAM SODIMM MT4VDDT1664H – 128MB MT4VDDT3264H – 256MB For the latest data sheet, please refer to the Micron site: www.micron.com/products/modules Figure 1: 200-Pin SODIMM (MO-224) 1.25in. (31.75mm) OPTIONS • Package 200-pin SODIMM (Standard) 200-pin SODIMM (Lead-free) • ...
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... MODULE PARTNUMBER DENSITY MT4VDDT1664HG-40B__ MT4VDDT1664HY-40B__ MT4VDDT3264HG-40B__ MT4VDDT3264HY-40B__ NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT4VDDT1664HG-40BA1. pdf: 09005aef80b56d1b, source: 09005aef8086ea0b DDA4C16_32x64HG.fm - Rev. D 9/04 EN 128MB, 256MB (x64, SR) PC3200 ...
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Table 3: Pin Assignment (200-Pin SODIMM Front) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 101 REF DQ19 103 SS 5 DQ0 55 DQ24 105 7 DQ1 57 V 107 DD 9 ...
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Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment tables on page 3 for more information PIN NUMBERS 118, 119, 120 WE#, CAS#, RAS# 35, 37, 158, 160 CK0, CK0#, CK1, CK1# 96 121 ...
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... V Supply Serial EEPROM positive power supply: +2.3V to +3.6V. DDSPD DNU — Do Not Use: These pins are not connected on these modules, but are assigned pins on other modules in this product family. NC — No Connect: These pins should be left unconnected. 5 DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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... DDR SDRAMs SA0 SA1 SA2 DDR SDRAMs DDR SDRAMs CK1 DDR SDRAMs U1, U2 CK1# Standard modules use the following DDR SDRAM devices: MT46V16M16TG (128MB); MT46V32M16TG (256MB) Lead-free modules use the following DDR SDRAM devices: MT46V16M16P (128MB); MT46V32M16P (256MB) 6 CS# UDQS UDM ...
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... DDR SDRAM modules use internally config- ured quad-bank DDR SDRAMs. DDR SDRAM modules use a double data rate archi- tecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-pre-fetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins ...
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Burst Length Read and write accesses to DDR SDRAM devices are burst oriented, with the burst length being program- mable, as shown in Figure 4, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that ...
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Table 6: Burst Definition Table STARTING BURST COLUMN ORDER OF ACCESSES LENGTH ADDRESS WITHIN A BURST TYPE = SEQUENTIAL 0 0-1-2 1-2-3 2-3-0 3-0-1-2 ...
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... Output Drive Strength The normal full drive strength for all outputs is specified to be SSTL2, Class II. The x16 DDR SDRAM devices used in these modules support an option for reduced drive. The reduced drive option is intended for lighter load and point-to-point environments. For detailed information on output drive strength options, refer to 256Mb or 512Mb DDR SDRAM component data sheets ...
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Commands Figure 8, Commands Truth Table, and Figure 9, DM Operation Truth Table, below, provide a general refer- ence of available commands. For a more detailed Table 8: Commands Truth Table CKE is HIGH for all commands shown except SELF ...
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Absolute Maximum Ratings Stresses greater than those listed may cause perma- nent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- ...
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Table 12: I Specifications and Conditions – 128MB Module DD DDR SDRAM component values only Notes: 1–5, 8, 10, 14, 48; notes appear on pages 17–20; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); ...
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Table 13: I Specifications and Conditions – 256MB Module DD DDR SDRAM component values only Notes: 1–5, 8, 10, 14, 48; notes appear on pages 17–20; 0°C PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge (MIN); ...
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Table 14: Capacitance Note: 11; notes appearon pages 17–20 PARAMETER Input/Output Capacitance: DQ, DQS, DM Input Capacitance: Command and Address, S#, CKE Input Capacitance: CK, CK# Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions Notes: 1–5, ...
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Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (Continued) Notes: 1–5, 12-15, 29; notes appear on pages 17–20; 0°C AC CHARACTERISTICS PARAMETER ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or ...
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Notes 1. All voltages referenced Tests for AC timing and electrical AC and DC DD characteristics may be conducted at nominal ref- erence/supply voltage levels, but the related spec- ifications and device operation are ...
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DRAM controller greater than eight refresh cycles is not allowed. 22. The valid data window is derived by achieving t t other specifications CK/2 QHS). The data ...
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Figure 7: Pull-Down Characteristics 160 140 120 100 0.0 0.5 1 (V) (V) OUT OUT Figure 9: Reduced Output Pull-Down Characteristics 0.0 0.5 1.0 ...
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The current Micron part operates below the slow- est JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 42. Random addressing changing and 50 percent of data changing at every transfer. 43. Random ...
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Initialization To ensure device operation the DRAM must be ini- tialized as described below: 1. Simultaneously apply power Apply V and then V power. REF TT 3. Assert and hold CKE at a LVCMOS logic low. 4. ...
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SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 12, Data Validity, and Figure ...
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Table 16: EEPROM Device Select Code Most significant bit (b7) is sent first SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code Table 17: EEPROM Operating Modes MODE Current Address Read Random Address Read Sequential Read Byte ...
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Table 18: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced DDSPD PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE 3mA ...
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Table 20: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” BYTE DESCRIPTION 0 Number of SPD Bytes Used by Micron 1 Total Number of Bytes in SPD Device 2 Fundamental Memory Type 3 Number of Row Addresses ...
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Table 20: Serial Presence-Detect Matrix (Continued) “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” BYTE DESCRIPTION 41 Min Active Auto Refresh Time, 42 Minimum Auto Refresh to Active/Auto Refresh t Command Period, RFC 43 SDRAM Device Max Cycle Time, 44 ...
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Figure 16: 200-Pin SODIMM Dimensions 0.079 (2.00) R (2X) U1 0.071 (1.80) (2X) 0.236 (6.00) 0.096 (2.44) 0.079 (2.00) 0.039 (.99) PIN 200 NOTE: All dimensions are in inches (millimeters); Data Sheet Designation Released (No Mark): This data sheet contains ...