HYS64T128021HDL-3S-B Qimonda, HYS64T128021HDL-3S-B Datasheet - Page 25

• Manufacturer Part Number: HYS64T128021HDL-3S-B
• Description: MODULE DDR2 1GB 200-SODIMM
• Manufacturer: Qimonda

Specifications of HYS64T128021HDL-3S-B

• Memory Type: DDR2 SDRAM
• Memory Size: 1GB
• Speed: 333MHz
• Package / Case: 200-SODIMM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 675-1026

2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
3.4
List of tables defining
Rev. 1.12, 2007-10
03292006-5LTN-QML0
Parameter
Operating Current 0
One bank Active - Precharge;
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
One bank Active - Read - Precharge;
t
control inputs are SWITCHING, Databus inputs are SWITCHING.
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH;
Data bus inputs are FLOATING.
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
t
SWITCHING; Data Bus inputs are SWITCHING;
Active Power-Down Current
All banks open;
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
Active Power-Down Current
All banks open; t
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Operating Current - Burst Read
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CL
t
bus inputs are SWITCHING;
Operating Current - Burst Write
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CL
t
SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
t
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
RCD
RAS
RP
RAS
CK
Both are measured from
12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if
=
=
=
=
=
t
t
RPMIN
CK.MIN
t
t
t
RAS.MAX
RAS.MAX.
RCD.MIN
; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
., Refresh command every
, AL = 0, CL = CL
,
,
t
t
t
RP
CK
CK
RP
=
=
=
=
I
t
t
t
I
t
RP.MIN
CK.MIN
CK.MIN
RP.MAX
DD
DD
Specifications and Conditions.
t
AOFD
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
Specifications and Conditions
; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
I
. Both are measured from
t
OUT
CK
MIN
=
= 0mA.
; CKE is HIGH, CS is HIGH between valid commands. Address and
t
CK.MIN
I
OUT
t
RFC
,
t
CK
t
t
= 0 mA, BL = 4,
RC
CK
=
=
t
=
=
t
RFC.MIN
CK.MIN
t
t
RC.MIN
CK.MIN
I
OUT
; Other control and address inputs are SWITCHING,
interval, CKE is HIGH, CS is HIGH between valid
t
,
; Other control and address inputs are STABLE,
AOFD
= 0 mA.
t
RAS
, which is interpreted differently per speed bin. For DDR2-400/533,
=
t
CK
t
25
RAS.MIN
=
t
MIN
CK.MIN
MIN
, CKE is HIGH, CS is HIGH between
;
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
;
t
t
CK
CK
,
t
t
CK
RC
=
=
= 5 ns.
t
t
CKMIN
=
CK.MIN
t
MIN
RC.MIN
;
;
;
t
t
RAS
CK
,
t
=
RAS
=
SO-DIMM DDR2 SDRAM Module
t
CK.MIN
t
RASMAX
=
I
DD
t
RAS.MIN
;
Measurement Conditions
;
,
Internet Data Sheet
Symbol Note
I
I
I
I
I
I
I
I
I
I
I
DD0
DD1
DD2N
DD2P
DD2Q
DD3N
DD3P(0)
DD3P(1)
DD4R
DD4W
DD5B
TABLE 18
3)4)5)
6)
6)
t
AOFD
1)2)
is