DS1972-F3+ Maxim Integrated Products, DS1972-F3+ Datasheet - Page 6

• Manufacturer Part Number: DS1972-F3+
• Description: IBUTTON EEPROM 1KBit F3
• Manufacturer: Maxim Integrated Products
• Series: iButton®r

Specifications of DS1972-F3+

• Rohs Information: IButton RoHS Compliance Plan
• Memory Size: 128B
• Memory Type: EEPROM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1024-Bit EEPROM iButton
commands is described in Figure 9. After a ROM
function command is successfully executed, the
memory functions become accessible and the master
can provide any one of the four memory function
commands. The protocol for these memory function
commands is described in Figure 7. All data is read
and written least significant bit first.
Each DS1972 contains a unique ROM code that is 64
bits long. The first 8 bits are a 1-Wire family code. The
next 48 bits are a unique serial number. The last 8 bits
are a cyclic redundancy check (CRC) of the first 56 bits.
See Figure 3 for details. The 1-Wire CRC is generated
Figure 3. 64-Bit Lasered ROM
Figure 4. 1-Wire CRC Generator
6
_______________________________________________________________________________________
X
0
MSB
MSB
STAGE
1ST
CRC CODE
X
1
8-BIT
STAGE
2ND
LSB
X
2
MSB
STAGE
64-Bit Lasered ROM
3RD
X
3
STAGE
4TH
POLYNOMIAL = X
48-BIT SERIAL NUMBER
X
4
8
+ X
5
STAGE
using a polynomial generator consisting of a shift regis-
ter and XOR gates as shown in Figure 4. The polynomial
is X
1-Wire CRC is available in Application Note 27:
Understanding and Using Cyclic Redundancy Checks
with Maxim iButton Products .
The shift register bits are initialized to 0. Then, starting
with the least significant bit of the family code, one bit
at a time is shifted in. After the 8th bit of the family code
has been entered, the serial number is entered. After
the last bit of the serial number has been entered, the
shift register contains the CRC value. Shifting in the 8
bits of the CRC returns the shift register to all 0s.
5TH
+ X
4
+ 1
8
+ X
5
+ X
4
X
5
+ 1. Additional information about the
STAGE
6TH
LSB
X
6
MSB
STAGE
7TH
8-BIT FAMILY CODE
(2Dh)
X
INPUT DATA
7
STAGE
8TH
LSB
LSB
X
8