KS8695X Micrel Inc, KS8695X Datasheet - Page 14

• Manufacturer Part Number: KS8695X
• Description: IC SWITCH 10/100 5PORT 208PQFP
• Manufacturer: Micrel Inc

Specifications of KS8695X

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 208-MQFP, 208-PQFP
• For Use With: KS8695-EVAL - EVAL KIT EXPERIMENTAL KS8695576-1005 - BOARD EVAL EXPERIMENT KS8695X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

KS8695X
M9999-102604
Functional Description
Introduction
The CENTAUR KS8695X is a cost-effective, high-performance router-on-a-chip solution for Ethernet-based systems. It
integrates a powerful processor with a 5-port switch that consists of five MAC units, five physical layer transceivers (PHYs),
DMA engines, and hardware protocol engines for CPU offloading.
The KS8695X is built around the 16/32-bit ARM922T RISC processor. The ARM922T is a scalable, high-performance,
microprocessor developed for highly integrated system-on-a-chip applications. The KS8695X offers an 8KB I-cache and an
8KB D-cache to reduce memory access latency for high-performance applications. There are also SDRAM, SRAM, and ROM
interfaces with configurable bus speeds and data width. The KS8695X provides external I/O interfaces, a UART interface, a
general purpose I/O, a JTAG debugging port, an internal interrupt controller, and internal timers.
The KS8695X contains independent DMA engines for the WAN and LAN. Each of the independent DMA engines supports
burst mode as well as little-endian byte ordering for memory buffers and descriptors. Each DMA engine contains one 3KB
receive FIFO and one 3KB transmit FIFO to ensure back-to-back packet reception and no under-runs on packet transmission.
An integrated switch provides hardware support for some of the most desirable Layer 2 features such as port-based VLAN,
QoS/CoS packet prioritization, IGMP snooping, and Spanning Tree Protocol. The switch contains a 16Kx32 SRAM on-chip
memory for frame buffering. The embedded frame buffer memory is designed with a 1.4Gbps on-chip memory bus. This allows
the KS8695X to perform full non-blocking frame switching and/or routing.
There are five MAC units in the KS8695X: four are for LAN and one is for the WAN.
Connected to the LAN and WAN MACs are five 10/100 PHYs. These PHYs use Micrel’s patented low-power analog PHY
technology to achieve increased performance. The PHY units also support the auto MDI/MDI-X feature. The LAN PHYs
support 10BASE-T and 100BASE-TX operation as per the IEEE802.3 standard. The WAN PHY supports 10BASE-T,
100BASE-TX, and 100BASE-FX operation.
The KS8695X combines proven PHY, MAC, and switch technology with protocol and DMA engines, and the powerful
ARM922T processor to create a solution that saves BOM costs, board real-estate, and design time while providing outstanding
performance for a variety of router applications.
CPU Features
• 166MHz ARM922T RISC processor core
• On-chip AMBA bus 2.0 interfaces
• 16-bit thumb programming to relax memory requirement
• 8KB I-cache and 8KB D-cache
• Little-endian mode supported
• Configurable memory management unit
• Supports reduced CPU and system clock speed for power saving
Advanced Memory Controller Features
• Supports glueless connection to two banks of ROM/SRAM/FLASH memory with programmable 8/16/32 bit data bus
• Supports glueless connection to two SDRAM banks with programmable 8/16/32 bit data bus and programmable
• Supports three external I/O banks with programmable 8/16/32 bit data bus and programmable access timing
• Programmable system clock speed for power management
Direct Memory Access (DMA) Engines
• Independent MAC DMA engine with programmable burst mode for WAN port
• Independent MAC DMA engine with programmable burst mode for LAN ports
• Supports little-endian byte ordering for memory buffers and descriptors
• Contains large independent receive and transmit FIFOs (3KB receive/3KB transmit) for back-to-back packet receive,
• Data alignment logic and scatter gather capability
XceleRouter Technology
• Supports IPv4 IP header/TCP/UDP Packet checksum generation for host CPU offloading
• Supports IPv4 packet filtering based on checksum errors
and programmable access timing
RAS/CAS latency
and guaranteed no under-run packet transmit
14
October 2004
Micrel