IDT88P8344BHGI IDT, Integrated Device Technology Inc, IDT88P8344BHGI Datasheet - Page 76

• Manufacturer Part Number: IDT88P8344BHGI
• Description: IC SPI3-SPI4 EXCHANGE 820-PBGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT88P8344BHGI

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 88P8344BHGI

timing register is used to manually align the phase of data lane n by adding from
0.1 clock cycle to 0.3 clock cycles of delay.
4 egress data lane n.
SPI-4 egress control lane timing register
(Block_base 0x0800 + Register_offset 0x2B)
TABLE 115 - SPI-4 EGRESS CONTROL LANE
TIMING REGISTER (REGISTER_OFFSET 0x2B)
and write access. The SPI-4 egress control lane timing register is used to
manually align the phase of the control lane by adding from 0.1 clock cycle to
0.3 clock cycles of delay.
SPI-4 egress control output.
SPI-4 egress data clock timing register
(Block_base 0x0800 + Register_offset 0x2C)
TABLE 116 - SPI-4 EGRESS DATA CLOCK TIMING
REGISTER (REGISTER_OFFSET 0x2C)
has read and write access. The SPI-4 egress data clock timing control register
is used to manually align the phase of the SPI-4 egress data clock to the data
and control lanes by adding from 0.1 clock cycle to 0.9 clock cycles of delay to
the data clock output. Note that tap selection is not monotonic with the number
in bit field [3:0].
SPI-4 egress data clock.
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
DTCn [1:0]
The SPI-4 egress control lane timing register at Block_base 0x0800 has read
CTLTC [1:0]
The SPI-4 egress data clock timing control register at Block_base 0x0800
DCTC [3:0] Used for adding 0.1 clock cycle units of output delay to the
CTLTC[1:0]
DCTC[3:0]
Field
Field
[1:0]=0=No added delay
[1:0]=1=Add 0.1 clock cycle of delay to data lane n
[1:0]=2=Add 0.2 clock cycles of delay to data lane n
[1:0]=3=Add 0.3 clock cycles of delay to data lane n
[1:0]=0=No added delay
[1:0]=1=Add 0.1 clock cycle of delay to the control output
[1:0]=2=Add 0.2 clock cycles of delay to the control output
[1:0]=3=Add 0.3 clock cycles of delay to the control output
[3:0]=0=No added delay
[3:0]=1=Add 0.1 clock cycle of delay to the SPI-4 egress data clock
[3:0]=3=Add 0.2 clock cycles of delay to the SPI-4 egress data clock
[3:0]=2=Add 0.3 clock cycles of delay to the SPI-4 egress data clock
[3:0]=7=Add 0.4 clock cycles of delay to the SPI-4 egress data clock
[3:0]=6=Add 0.5 clock cycles of delay to the SPI-4 egress data clock
[3:0]=4=Add 0.6 clock cycles of delay to the SPI-4 egress data clock
[3:0]=5=Add 0.7 clock cycles of delay to the SPI-4 egress data clock
[3:0]=F=Add 0.8 clock cycles of delay to the SPI-4 egress data clock
[3:0]=E=Add 0.9 clock cycles of delay to the SPI-4 egress data clock
Used for adding 0.1 clock cycle units of output delay to SPI-
Used for adding 0.1 clock cycle units of output delay to the
Bits
Bits
1:0
3:0
Length
Length
2
4
Initial Value
Initial Value
0
0
76
SPI-4 egress status timing register (Block_base
0x0800 + Register_offset 0x2D)
TABLE 117 - SPI-4 EGRESS STATUS TIMING
REGISTER (REGISTER_OFFSET 0x2D)
0x2D has read and write access. The SPI-4 egress status timing register is used
to manually align the phase of the status lane n by adding from 0.1 clock cycle
to 0.3 clock cycles of delay. The STC0[1:0] and STC0[1:0] fields are valid only
for LVDS status, not for LVTTL status.
4 egress status lane n.
SPI-4 egress status clock timing register
(Block_base 0x0800 + Register_offset 0x2E)
TABLE 118 - SPI-4 EGRESS STATUS CLOCK TIM-
ING REGISTER (REGISTER_OFFSET 0x2E)
Register_offset 0x2E has read and write access. The SPI-4 egress status clock
timing register is used to manually align the phase of the SPI-4 egress status clock
to the status outputs by adding from 0.1 clock cycle to 0.9 clock cycles of delay
to the status clock output. Note that tap selection is not monotonic with the number
in bit field [3:0]. The SCTC[3:0] field is valid only for LVDS status, not for LVTTL
status.
4 egress status clock output.
The SPI-4 egress status timing register at Block_base 0x0800 + Register_offset
STCn [1:0]
The SPI-4 egress status clock timing register at Block_base 0x0800 +
SCTC [3:0]
STC0[1:0]
STC1[1:0]
SCTC[3:0]
Field
Field
[1:0]=0=No added delay
[1:0]=1=Add 0.1 clock cycle of delay to status lane n
[1:0]=2=Add 0.2 clock cycles of delay to status lane n
[1:0]=3=Add 0.3 clock cycles of delay to status lane n
[3:0]=0=No added delay
[3:0]=1=Add 0.1 clock cycle of delay t o the SPI-4 egress status clock
[3:0]=3=Add 0.2 clock cycles of delay to the SPI-4 egress status clock
[3:0]=2=Add 0.3 clock cycles of delay to the SPI-4 egress status clock
[3:0]=7=Add 0.4 clock cycles of delay to the SPI-4 egress status clock
[3:0]=6=Add 0.5 clock cycles of delay to the SPI-4 egress status clock
[3:0]=4=Add 0.6 clock cycles of delay to the SPI-4 egress status clock
[3:0]=5=Add 0.7 clock cycles of delay to the SPI-4 egress status clock
[3:0]=F=Add 0.8 clock cycles of delay to the SPI-4 egress status clock
[3:0]=E=Add 0.9 clock cycles of delay to the SPI-4 egress status clock
Used for adding 0.1 clock cycle units of output delay to SPI-
Used for adding 0.1 unit intervals of output delay to the SPI-
Bits
Bits
1:0
3:2
3:0
INDUSTRIAL TEMPERATURE RANGE
Length
Length
2
2
4
APRIL 10, 2006
Initial Value
Initial Value
0
0
0