IDT72P51769L6BBI IDT, Integrated Device Technology Inc, IDT72P51769L6BBI Datasheet - Page 28

• Manufacturer Part Number: IDT72P51769L6BBI
• Description: IC FLOW CTRL 36BIT 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51769L6BBI

• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 3.7ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 166MHz
• Supply Current: 150mA
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51769L6BBI

as well as the next word from the new queue (Q
through to the output register (provided the OE is asserted) consecutively
(cycles “F” and “G” respectively) following the selection of the new queue
regardless of the state of REN, unless the new queue (Q
selected queue is empty, any reads from that queue will be prevented. Data
cannot be read from an empty queue. Remember that OE allows the user to
place the data output bus (Qout) into High-Impedance and the data can be read
in to the output register regardless of OE.
13, 15, and 16 for read queue selection and read port operation timing diagrams.
PACKET MODE OPERATION
packets or frames can be written to the device as opposed to Standard mode
where individual words are written. For clarification, in Packet Mode, a packet
can be written to the device with the starting location designated as Transmit Start
of Packet (TSOP) and the ending location designated as Transmit End of Packet
(TEOP). In conjunction, a packet read from the device will be designated as
Receive Start of Packet (RSOP) and a Receive End of Packet (REOP). The
minimum size for a packet is four words (SOP, two words of data and EOP). The
4 words must be the largest word that is configured. For example in a x18 to
x9 bus matching configuration the four words must be x18 bit words. The almost
empty flag bus becomes the “Packet Ready” PR flag bus when the device is
configured for packet mode. Valid packets are indicated when both PR and OR
are asserted.
WRITE QUEUE SELECTION AND WRITE OPERATION (PACKET MODE)
Writing in Packet Mode during a Queue Change). WADEN goes high signaling
a change of queue (clock cycle “B” or “I”). The address on WRADD at the rising
edge of WCLK determines the next queue. Data presented on Din during that
cycle (“B” or “I”) and the next cycle (“C” or “J”) can continue to be written to
the active (old) queue (Q
If WEN is HIGH (inactive) for these two clock cycles (H), data will not be written
in to the previous queue (Q
the full status of the newly selected queue (Q
or “K”). Data values presented on the data input bus (Din), can be written into
the newly selected queue (Q
(“E”) following a request for change of queue, provided WEN is LOW (active)
IDT72P51749/72P51759/72P51769 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648, 2,359,296, and 4,718,592 bits
Refer to Table 5, for Read Address Bus arrangement. Also, refer to Figures
The Packet mode operation provides the capability where, user defined
Changing queues requires 4 WCLK cycles on the write port (see Figure 54,
A
or Q
A
). The write port discrete full flag will update to show
X
B
) on the rising edge of WCLK on the third cycle
respectively), provided WEN is LOW (active).
B
) at this last cycle’s rising edge (“D”
F
). Both of these words will fall
F
) is empty. If the newly
28
and the new queue is not full. If a selected queue is full (FF is LOW), then writes
to that queue will be prevented. Note, data cannot be written into a full queue.
diagrams.
READ QUEUE SELECTION AND READ OPERATION (PACKET MODE)
Reading in Packet Mode during a Queue Change). RADEN goes high
signaling a change of queue (clock cycle “B” or “I”). The address on RDADD
at the rising edge of RCLK determines the queue. As illustrated in Figure 55
during cycle (“B” or “I”), and the next cycle (“C” or “J”) data can continue to
be read from the active (old) queue (Q
and OE are LOW (active) simultaneously with changing queues. In applications
where the multi-queue flow-control device is connected to a shared bus, an
output enable, OE control pin is also provided to allow High-Impedance selection
of the data outputs (Qout).
well as Figure 38, 39, 40, 41, and 42 for timing diagrams and Table 5, for Read
Address bus arrangement.
the device is configured for packet ready mode.
EXPANDING UP TO 256 QUEUES OR PROVIDING DEEPER QUEUES
queue device, the WRADD address bus is 8 bits wide. The 7 Least Significant
bits (LSbs) are used to address one of the 128 available queues within a single
multi-queue device. The Most Significant bit (MSbs) is used when a device is
connected in expansion configuration with up to 2 devices connected in width
expansion, each device having its own bit address. When logically expanded
with multiple parts, each device is statically setup with a unique chip ID code on
the ID pins, ID0, ID1, and ID2. A device is selected when the Most Significant
bit of the WRADD address bus matches the ID code. The maximum logical
expansion is 256 queues (128 queues x 2 devices).
bus strobe), to address the almost full flag bus during direct mode of operation.
47, Full Flag Timing Expansion Configuration, Figure 51, Output Ready Flag
Timing (In Expansion Configuration), and Figure 67, Expansion using ID
codes, for timing diagrams.
Refer to Figure 54, Writing in Packet Mode during a Queue Change for timing
Changing queues requires 4 RCLK cycles on the read port (see Figure 55,
Refer to Figure 55, Reading in Packet Mode during a Queue Change as
Note, the almost empty flag bus becomes the “Packet Ready” flag bus when
Expansion can take place only in IDT Standard mode. In the 128 queue multi-
Note: The WRADD bus is also used in conjunction with FSTR (almost full flag
Refer to Table 4, for Write Address bus arrangement. Also, refer to Figure
A
COMMERCIAL AND INDUSTRIAL
or Q
B
respectively), provided both REN
TEMPERATURE RANGES
SEPTEMBER 27, 2004