IDT72P51769L6BB IDT, Integrated Device Technology Inc, IDT72P51769L6BB Datasheet - Page 26

• Manufacturer Part Number: IDT72P51769L6BB
• Description: IC FLOW CTRL 36BIT 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51769L6BB

• Configuration: Dual
• Density: 4.5Mb
• Access Time (max): 3.7ns
• Word Size: 36b
• Sync/async: Synchronous
• Expandable: Yes
• Bus Direction: Uni-Directional
• Package Type: BGA
• Clock Freq (max): 166MHz
• Supply Current: 150mA
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51769L6BB

TABLE 4 — WRITE ADDRESS BUS, WRADD[7:0]
STANDARD MODE OPERATION
WRITE QUEUE SELECTION AND WRITE OPERATION
(STANDARD MODE)
can be configured up to a maximum of 128 queues which data can be written
via a common write port using the data inputs (Din), write clock (WCLK) and
write enable (WEN). The queue to be written is selected by the address present
on the write address bus (WRADD) during a rising edge on WCLK while write
address enable (WADEN) is HIGH. The state of WEN does not impact the queue
selection. The queue selection requires 4 WCLK cycle. All subsequent data
writes will be to this queue until another queue is selected.
device as opposed to Packet Mode where complete packets are written. The
write port is designed such that 100% bus utilization can be obtained. This
means that data can be written into the device on every WCLK rising edge
including the cycle that a new queue is being addressed.
IDT72P51749/72P51759/72P51769 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 36 BIT WIDE CONFIGURATION 1,179,648, 2,359,296, and 4,718,592 bits
The IDT72P51749/72P51759/72P51769 multi-queue flow-control devices
Standard mode operation is defined as individual words will be written to the
Quadrant
Operation WCLK WADEN FSTR
Queue
Select
Select
PAFn
Write
Status Word
1
0
Address
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
26
Write Queue Select, Write Operation and Full flag Operation). WADEN goes
high signaling a change of queue (clock cycle “A”). The address on WRADD
at that time determines the next queue. Data presented during that cycle (“A”)
and the next cycle (“B” and “C”), will be written to the active (old) queue,
provided WEN is LOW. If WEN is HIGH (inactive) for these 3 clock cycles, data
will not be written in a queue. The write port discrete full flag will update to show
the full status of the newly selected queue (Q
Data present on the data input bus (Din), can be written into the newly selected
queue (Q
change of queue, provided WEN is LOW and the new queue is not full. If the
newly selected queue is full at the point of its selection, any writes to that queue
will be prevented. Data cannot be written into a full queue.
Operation, Figure 46, Write Operations in First Word Fall Through for timing
diagrams and Figure 47, Full Flag Timing in Expansion Configuration for timing
diagrams.
0
1
Changing queues requires 4 WCLK cycles on the write port (see Figure 44,
Refer to Figure 44, Write Queue Select, Write Operation and Full flag
Queue Status on PAFn Bus
Q0 : Q7 → PAF0 : PAF7
Q8 : Q15 → PAF0 : PAF7
Q16 : Q23 → PAF0 : PAF7
Q24 : Q31 → PAF0 : PAF7
Q32 : Q39 → PAF0 : PAF7
Q40 : Q47 → PAF0 : PAF7
Q48 : Q55 → PAF0 : PAF7
Q56 : Q63 → PAF0 : PAF7
Q64 : Q71 → PAF0 : PAF7
Q72 : Q79 → PAF0 : PAF7
Q80 : Q87 → PAF0 : PAF7
Q88 : Q95 → PAF0 : PAF7
Q96 : Q103 → PAF0 : PAF7
Q104 : Q111 → PAF0 : PAF7
Q112 : Q119 → PAF0 : PAF7
Q120 : Q127 → PAF0 : PAF7
Device Select
(Compared to
ID0,1,2)
Device Select
(Compared to
ID0,1,2)
X
) on the rising edge of WCLK on the third cycle (“D”) following a
7 6 5
7 6 5
WRADD[7:0]
Write Queue Address
(6 bits = 64 Queues
7 bits = 128 Queues)
4 3 2
4
X
3 2 1 0
Status Word
Address
COMMERCIAL AND INDUSTRIAL
6714
X
) at this last cycle’s rising edge (“C”).
1 0
drw11
TEMPERATURE RANGES
SEPTEMBER 27, 2004