IDT89HPES48T12ZABR IDT, Integrated Device Technology Inc, IDT89HPES48T12ZABR Datasheet - Page 5

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IDT89HPES48T12ZABR

Manufacturer Part Number
IDT89HPES48T12ZABR
Description
IC PCI SW 48LANE 12PORT 1156BGA
Manufacturer
IDT, Integrated Device Technology Inc

Specifications of IDT89HPES48T12ZABR

Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Operating Temperature (max)
70C
Package Type
FCBGA
Rad Hardened
No
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
89HPES48T12ZABR

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
IDT89HPES48T12ZABR
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
IDT 89HPES48T12 Data Sheet
MSMBADDR[4:1]
REFCLKP[3:0]
REFCLKN[3:0]
PE10RP[3:0]
PE10RN[3:0]
PE10TN[3:0]
PE11RP[3:0]
PE11RN[3:0]
PE11TN[3:0]
PE10TP[3:0]
PE11TP[3:0]
PE8RN[3:0]
PE9RN[3:0]
PE7TP[3:0]
PE7TN[3:0]
PE8RP[3:0]
PE8TP[3:0]
PE8TN[3:0]
PE9RP[3:0]
PE9TP[3:0]
PE9TN[3:0]
MSMBCLK
MSMBDAT
REFCLKM
Signal
Signal
Type
Type
I/O
I/O
O
O
O
O
O
I
I
I
I
I
I
I
Table 2 PCI Express Interface Pins (Part 2 of 2)
PCI Express Port 7 Serial Data Transmit. Differential PCI Express transmit pairs for
port 7. When port 6 is merged with port 7, these signals become port 6 transmit pairs
for lanes 4 through 7.
PCI Express Port 8 Serial Data Receive. Differential PCI Express receive pairs for
port 8.
PCI Express Port 8 Serial Data Transmit. Differential PCI Express transmit pairs for
port 8.
PCI Express Port 9 Serial Data Receive. Differential PCI Express receive pairs for
port 9. When port 8 is merged with port 9, these signals become port 8 receive pairs
for lanes 4 through 7.
PCI Express Port 9 Serial Data Transmit. Differential PCI Express transmit pairs for
port 9. When port 8 is merged with port 9, these signals become port 8 transmit pairs
for lanes 4 through 7.
PCI Express Port 10 Serial Data Receive. Differential PCI Express receive pairs for
port 10.
PCI Express Port 10 Serial Data Transmit. Differential PCI Express transmit pairs
for port 10.
PCI Express Port 11 Serial Data Receive. Differential PCI Express receive pairs for
port 11. When port 10 is merged with port 11, these signals become port 10 receive
pairs for lanes 4 through 7.
PCI Express Port 11 Serial Data Transmit. Differential PCI Express transmit pairs
for port 11. When port 10 is merged with port 11, these signals become port 10 trans-
mit pairs for lanes 4 through 7.
PCI Express Reference Clock Mode Select. This signal selects the frequency of the
reference clock input.
0x0 - 100 MHz
0x1 - 125 MHz
PCI Express Reference Clock. Differential reference clock pair input. This clock is
used as the reference clock by on-chip PLLs to generate the clocks required for the
system logic and on-chip SerDes. The frequency of the differential reference clock is
determined by the REFCLKM signal.
Master SMBus Address. These pins determine the SMBus address of the serial
EEPROM from which configuration information is loaded.
Master SMBus Clock. This bidirectional signal is used to synchronize transfers on the
master SMBus. It is active and generating the clock only when the EEPROM or I/O
Expanders are being accessed.
Master SMBus Data. This bidirectional signal is used for data on the master SMBus.
Table 3 SMBus Interface Pins (Part 1 of 2)
5 of 47
Name/Description
Name/Description
October 7, 2008

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