IDT72P51767L6BB IDT, Integrated Device Technology Inc, IDT72P51767L6BB Datasheet - Page 30

• Manufacturer Part Number: IDT72P51767L6BB
• Description: IC FLOW CTRL 40BIT 376-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72P51767L6BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72P51767L6BB

PLL ON VS PLL OFF MODES
the access time (ta) for the DDR. Below 85MHz or in SDR mode, the PLL must
be turned off. The following diagrams show the difference between the two
modes:
NOTES:
1. Echo clocks are center aligned.
2. ERCLK is aligned with internal PLL generated clock.
3. QOUT is clocked out 1 cycle after valid REN.
4. Data Access time (Ta) is +/-1.0ns when PLL is on, with respect to rising edges of RCLK (1 Clock Latency).
NOTES:
1. ERCLK has uncontrollable delay when PLL is off.
2. DOUT is clocked out 1 cycle after valid REN.
3. Data Access time (Ta) is <3.6ns when PLL is off, with respect to rising/falling edges of RCLK.
IDT72P51767/72P51777 1.8V, MULTI-QUEUE FLOW-CONTROL DEVICES
(128 QUEUES) 40 BIT WIDE CONFIGURATION 5,898,240 and 11,796,480 bits
The PLL has a frequency response rate of 85-166MHz. The PLL reduces
QOUT
(PLL off)
ERCLK
EREN
RCLK
QOUT
(PLL on)
REN
PAE
ERCLK
ERCLK
EREN
EF
RCLK
REN
t
ERCLK
Figure 8. DDR Read Operation with PLL OFF
Figure 7. DDR Read Operation with PLL ON
t
A
t
A
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
6724 drw09c
FEBRUARY 11, 2009
6724 drw09b