IDT89HPES22H16ZABCGI8 IDT, Integrated Device Technology Inc, IDT89HPES22H16ZABCGI8 Datasheet - Page 3
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IDT89HPES22H16ZABCGI8
Manufacturer Part Number
IDT89HPES22H16ZABCGI8
Description
IC PCI SW 22LANE 16PORT 484CABGA
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.IDT89HPES22H16ZABC8.pdf
(36 pages)
Specifications of IDT89HPES22H16ZABCGI8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
89HPES22H16ZABCGI8
Hot-Plug Interface
device, the PES22H16 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface. Following
reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES22H16 generates an SMBus transaction to the I/O
expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is received on
the IOEXPINTN input pin (alternate function of GPIO) of the PES22H16. In response to an I/O expander interrupt, the PES22H16 generates an
SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.
General Purpose Input/Output
outputs, or alternate functions. Some GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software,
SMBus slave interface, or serial configuration EEPROM.
Pin Description
The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)
level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level. Differ-
ential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the positive portion of the differential pair and the differential signal
ending in “N” is the negative portion of the differential pair.
IDT 89HPES22H16 Data Sheet
The PES22H16 supports PCI Express Hot-Plug on each downstream port (ports 1 through 15). To reduce the number of pins required on the
The PES22H16 provides 32 General Purpose I/O (GPIO) pins that may be individually configured as general purpose inputs, general purpose
The following tables lists the functions of the pins provided on the PES22H16. Some of the functions listed may be multiplexed onto the same pin.
(a) Unified Configuration and Management Bus
PES22H16
PE0RN[3:0]
PE2RN[3:0]
PE0RP[3:0]
PE0TP[3:0]
PE0TN[3:0]
PE2RP[3:0]
PE2TP[3:0]
PE2TN[3:0]
PE1RP[0]
PE1RN[0]
PE1TN[0]
PE1TP[0]
Signal
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
Processor
SMBus
Master
Type
O
O
O
I
I
I
EEPROM
Figure 3 SMBus Interface Configuration Examples
Serial
Table 2 PCI Express Interface Pins (Part 1 of 3)
PCI Express Port 0 Serial Data Receive. Differential PCI Express receive pairs for
port 0. Port 0 is the upstream port.
PCI Express Port 0 Serial Data Transmit. Differential PCI Express transmit pairs for
port 0. Port 0 is the upstream port.
PCI Express Port 1 Serial Data Receive. Differential PCI Express receive pair for
port 1.
PCI Express Port 1 Serial Data Transmit. Differential PCI Express transmit pair for
port 1.
PCI Express Port 2 Serial Data Receive. Differential PCI Express receive pairs for
port 2.
PCI Express Port 2 Serial Data Transmit. Differential PCI Express transmit pairs for
port 2.
...
Devices
SMBus
Other
3 of 36
Name/Description
(b) Split Configuration and Management Buses
PES22H16
MSMBCLK
MSMBDAT
SSMBCLK
SSMBDAT
Processor
SMBus
Master
EEPROM
Serial
...
Devices
SMBus
Other
October 21, 2009