IDT72V51356L7-5BB IDT, Integrated Device Technology Inc, IDT72V51356L7-5BB Datasheet - Page 21

• Manufacturer Part Number: IDT72V51356L7-5BB
• Description: IC FLOW CTRL MULTI QUEUE 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT72V51356L7-5BB

• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 72V51356L7-5BB

TABLE 5 — PACKET MODE VALID BYTE
NOTE:
they enter respective queues via the write port and as they exit queues via
the read port. The multi-queue internal logic increments and decrements a
packet counter, which is provided for each queue. The functionality of the
packet ready logic provides status as to whether at least one full packet of data
is available within the selected queue. A partial packet in a queue is regarded
as a packet not ready and PR (active LOW) will be HIGH. In Packet mode, no
words can be read from a queue until at least one complete packet has been
written into the queue, regardless of REN. For example, if a TSOP has been
written and some number of words later a TEOP is written a full packet of data
is deemed to be available, and the PR flag and OV will go active LOW.
Consequently if reads begin from a queue that has only one complete packet
and the RSOP is detected on the output port as data is being read out, PR will
go inactive HIGH. OV will remain LOW indicating there is still valid data being
read out of that queue until the REOP is read. The user may proceed with the
reading operation until the current packet has been read out and no further
complete packets are available. If during that time another complete packet has
been written into the queue and the PR flag will again gone active, then reads
from the new packet may follow after the current packet has been completely
read out.
end of packet markers and regard data in between the TSOP and TEOP as
a full packet of data. The packet monitoring has no limitation as to how many
packets are written into a queue, the only constraint is the depth of the queue.
Note, there is a minimum allowable packet size of four words, inclusive of the
TSOP marker and TEOP marker.
marker.
regards data between the first TSOP and the first subsequent TEOP as the full
packet. The same is true for TEOP; a second consecutive TEOP mark is
ignored. On the read side the user should regard a packet as being between
the first RSOP and the first subsequent REOP and disregard consecutive
RSOP markers and/or REOP markers. This is why a TEOP may be written
twice, using the second TEOP as the filler word.
End of Packet” (AEOP) marker. For example, the AEOP can be assigned to
data input bit D33. The purpose of this AEOP marker is to provide an indicator
IDT72V51336/72V51346/72V51356 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(8 QUEUES) 36 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
Packet Mode is only available when the Input Port and Output Port are 36 bits wide.
The packet ready logic monitors all start and end of packet markers both as
The packet counters therefore look for start of packet markers followed by
The packet logic does expect a TSOP marker to be followed by a TEOP
If a second TSOP marker is written after a first, it is ignored and the logic
As an example, the user may also wish to implement the use of an “Almost
TMOD1 (D33)
RMOD1 (Q33)
0
0
1
1
BYTE D
TMOD2 (D32)
RMOD2 (Q32)
BYTE C
0
1
0
1
21
that the end of packet is a fixed (known) number of reads away from the end
of packet. This is a useful feature when due to latencies within the system,
monitoring the REOP marker alone does not prevent “over reading” of the data
from the queue selected. For example, an AEOP marker set 4 writes before
the TEOP marker provides the device connected to the read port with and
“almost end of packet” indication 4 cycles before the end of packet.
The AEOP can be set any number of words before the end of packet determined
by user requirements or latencies involved in the system.
18, Data Input (Transmit) Packet Mode of Operation and Figure 19, Data
Output (Receive) Packet Mode of Operation.
PACKET MODE – MODULO OPERATION
modulo bits, they are only informational bits that are passed through with the
respective data byte(s).
may also want to consider the implementation of “Modulo” operation or “valid
byte marking”. Modulo operation may be useful when the packets being
transferred through a queue are in a specific byte arrangement even though
the data bus width is 36 bits. In Modulo operation the user can concatenate bytes
to form a specific data string through the multi-queue device. A possible scenario
is where a limited number of bytes are extracted from the packet for either
analysis or filtered for security protection. This will only occur when the first 36
bit word of a packet is written in and the last 36 bit word of packet is written in.
The modulo operation is a means by which the user can mark and identify
specific data within the Queue.
D33 (transmit modulo bit 1, TMOD1) can be used as data markers. An example
of this could be to use D32 and D33 to code which bytes of a word are part
of the packet that is also being marked as the “Start of Marker” or “End of
Marker”. Conversely on the read port when reading out these marked words,
data outputs Q32 (receive modulo bit 2, RMOD2) and Q33 (receive modulo
bit 1, RMOD1) will pass on the byte validity information for that word. Refer to
Table 5 for one example of how the modulo bits may be setup and used. See
Figure 18, Data Input (Transmit) Packet Mode of Operation and Figure 19,
Data Output (Receive) Packet Mode of Operation.
See Figure 17, Reading in Packet Mode during a Queue Change, Figure
The internal packet ready control logic performs no operation on these
When utilizing the multi-queue flow-control device in packet mode, the user
On the write port data input bits, D32 (transmit modulo bit 2, TMOD2) and
BYTE B
VALID BYTES
A, B, C, D
A
A, B
A, B, C
BYTE A
5936 drw07
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES